| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | at91-sama5d2_adc.txt | 4 - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
5 - reg: Should contain ADC registers location and length.
6 - interrupts: Should contain the IRQ line for the ADC.
7 - clocks: phandle to device clock.
8 - clock-names: Must be "adc_clk".
9 - vref-supply: Supply used as reference for conversions.
10 - vddana-supply: Supply for the adc device.
11 - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
12 - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
13 - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/ |
| D | atmel,sama5d2-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
15 - atmel,sama5d2-adc
16 - microchip,sam9x60-adc
17 - microchip,sama7g5-adc
28 clock-names:
31 vref-supply: true
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-tqmx86.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TQ-Systems TQMx86 PLD GPIO driver
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
35 /* Stored in irq_type as a trigger type, but not actually valid as a register
56 return ioread8(gd->io_base + reg); in tqmx86_gpio_read()
62 iowrite8(val, gd->io_base + reg); in tqmx86_gpio_write()
78 raw_spin_lock_irqsave(&gpio->spinlock, flags); in tqmx86_gpio_set()
79 __assign_bit(offset, gpio->output, value); in tqmx86_gpio_set()
[all …]
|
| D | gpio-mxc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
34 /* device type dependent stuff */
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
[all …]
|
| D | gpio-omap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/kernel/apic/ |
| D | io_apic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
94 int trigger; member
111 * Saved state during suspend/resume, or while enabling intr-remap.
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-mxc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
34 /* device type dependent stuff */
81 .edge_sel_reg = -EINVAL,
96 .edge_sel_reg = -EINVAL,
121 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
122 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
123 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
124 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
125 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
[all …]
|
| D | gpio-omap.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
18 to be driven per N output. An Interrupt Router can either handle edge
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
|
| D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
18 to be driven per N output. An Interrupt Router can either handle edge
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
|
| D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
[all …]
|
| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | asic3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2004-2005 Phil Blundell
9 * Copyright 2007-2008 OpenedHand Ltd.
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
122 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | qcom-pm8xxx.txt | 1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
10 Value type: <string>
16 - #address-cells:
18 Value type: <u32>
21 - #size-cells:
23 Value type: <u32>
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/cavium/ |
| D | ciu3.txt | 4 - compatible: "cavium,octeon-7890-ciu3"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is source number.
14 value of either 4 for level semantics, or 1 for edge semantics.
17 interrupt-controller@1010000000000 {
18 compatible = "cavium,octeon-7890-ciu3";
19 interrupt-controller;
22 * 2) Trigger type: (4 == level, 1 == edge)
24 #address-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/ |
| D | ciu3.txt | 4 - compatible: "cavium,octeon-7890-ciu3"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is source number.
14 value of either 4 for level semantics, or 1 for edge semantics.
17 interrupt-controller@1010000000000 {
18 compatible = "cavium,octeon-7890-ciu3";
19 interrupt-controller;
22 * 2) Trigger type: (4 == level, 1 == edge)
24 #address-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | brcm,kona-gpio.txt | 9 GPIO controller only supports edge, not level, triggering of interrupts.
12 -------------------
14 - compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
15 - reg: Physical base address and length of the controller's registers.
16 - interrupts: The interrupt outputs from the controller. There is one GPIO
21 - #gpio-cells: Should be <2>. The first cell is the pin number, the second
23 - bit 0 specifies polarity (0 for normal, 1 for inverted)
24 See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
25 - #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
28 - trigger type (bits[1:0]):
[all …]
|
| D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
|
| /kernel/linux/linux-6.6/drivers/comedi/drivers/ |
| D | addi_apci_1500.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
23 * PCI Bar 0 Register map (devpriv->amcc)
28 * PCI Bar 1 Register map (dev->iobase)
[all …]
|
| D | amplc_pci230.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * COMEDI - Linux Control and Measurement Device Interface
35 * --------- ---------
43 * The AI subdevice has 16 single-ended channels or 8 differential
46 * The PCI230 and PCI260 cards have 12-bit resolution. The PCI230+ and
47 * PCI260+ cards have 16-bit resolution.
51 * or PCI260 then it actually uses a "pseudo-differential" mode where the
62 * 0 => [-10, +10] V
63 * 1 => [-5, +5] V
64 * 2 => [-2.5, +2.5] V
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | addi_apci_1500.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
23 * PCI Bar 0 Register map (devpriv->amcc)
28 * PCI Bar 1 Register map (dev->iobase)
[all …]
|
| D | amplc_pci230.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * COMEDI - Linux Control and Measurement Device Interface
35 * --------- ---------
43 * The AI subdevice has 16 single-ended channels or 8 differential
46 * The PCI230 and PCI260 cards have 12-bit resolution. The PCI230+ and
47 * PCI260+ cards have 16-bit resolution.
51 * or PCI260 then it actually uses a "pseudo-differential" mode where the
62 * 0 => [-10, +10] V
63 * 1 => [-5, +5] V
64 * 2 => [-2.5, +2.5] V
[all …]
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
21 machine type that we currently have.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
37 SMC9196 interrupts until it has finished transferring its multi-sector
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
21 machine type that we currently have.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
36 IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
37 SMC9196 interrupts until it has finished transferring its multi-sector
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
|