Searched +full:two +full:- +full:lane (Results 1 – 25 of 340) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
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| D | ti,omap3isp.txt | 4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.txt | 4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
49 between two devices, e.g. there are logic signal inverters on the lines.
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
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| D | ti,omap3isp.txt | 4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
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| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/ |
| D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
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| D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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| /kernel/linux/linux-6.6/include/linux/platform_data/media/ |
| D | omap4iss.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
29 * @data: Configuration of one or two data lanes
30 * @clk: Clock lane configuration
38 * struct iss_csi2_platform_data - CSI2 interface platform data
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| /kernel/linux/linux-5.10/include/linux/platform_data/media/ |
| D | omap4iss.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct iss_csiphy_lane: CSI2 lane position and polarity
16 * @pos: position of the lane
17 * @pol: polarity of the lane
28 * struct iss_csiphy_lanes_cfg - CSI2 lane configuration
29 * @data: Configuration of one or two data lanes
30 * @clk: Clock lane configuration
38 * struct iss_csi2_platform_data - CSI2 interface platform data
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| /kernel/linux/linux-6.6/drivers/platform/x86/intel/pmc/ |
| D | spt.c | 1 // SPDX-License-Identifier: GPL-2.0
22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
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| /kernel/linux/linux-6.6/Documentation/driver-api/nvdimm/ |
| D | btt.rst | 2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
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| /kernel/linux/linux-5.10/Documentation/driver-api/nvdimm/ |
| D | btt.rst | 2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/ti/omap3isp/ |
| D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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| /kernel/linux/linux-5.10/drivers/media/platform/omap3isp/ |
| D | omap3isp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | uncore-io.json | 94 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
100 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
111 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
122 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
133 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
144 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
155 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
166 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
177 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-io.json | 12 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
27 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
140 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
151 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
162 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
173 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
184 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
195 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/ |
| D | link_service_types.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
69 /* TODO: turn lane settings below into mandatory fields
70 * as initial lane configuration
76 /* TODO - factor lane_settings out because it changes during LT */
93 /* disallow different lanes to have different lane settings */
95 /* dpcd lane settings will always use the same hw lane settings
96 * even if it doesn't match requested lane adjust */
100 * training states - parameters that can change in link training
103 * along with lane adjust, lane align, offset and all
106 * a constant input pre-decided prior to link training.
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
43 * IOSF-SB port.
45 * Each display PHY is made up of one or two channels. Each channel
46 * houses a common lane part which contains the PLL and other common
47 * logic. CH0 common lane also contains the IOSF-SB logic for the
56 * Eeach channel also has two splines (also called data lanes), and
57 * each spline is made up of one Physical Access Coding Sub-Layer
58 * (PCS) block and two TX lanes. So each channel has two PCS blocks
62 * Additionally the PHY also contains an AUX lane with AUX blocks
68 * Generally on VLV/CHV the common lane corresponds to the pipe and
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
41 * Each display PHY is made up of one or two channels. Each channel
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
52 * Eeach channel also has two splines (also called data lanes), and
53 * each spline is made up of one Physical Access Coding Sub-Layer
54 * (PCS) block and two TX lanes. So each channel has two PCS blocks
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | ti-pci.txt | 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
[all …]
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