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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
17 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
22 - ti,am654-icssg-prueth # for AM65x SoC family
32 dma-names:
34 - const: tx0-0
[all …]
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
22 Complex (UDMA-P) controller.
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
27 #define DP_PHY_CFG 0x0010
28 #define DP_PHY_CFG_1 0x0014
29 #define DP_PHY_PD_CTL 0x001c
30 #define DP_PHY_MODE 0x0020
32 #define DP_PHY_AUX_CFG0 0x0024
33 #define DP_PHY_AUX_CFG1 0x0028
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/
Dsja1000.txt5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
8 to map the registers of the SJA1000. The size is usually 0x80.
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
27 <0x1> : normal output mode (default)
28 <0x2> : test output mode
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
11 reg = <0 0x2c000000 0 0x1000000>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
17 reg = <0x2d000000 0x20000>;
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
[all …]
/kernel/linux/linux-6.6/sound/firewire/dice/
Ddice-alesis.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-alesis.c - a part of driver for DICE based devices
12 {6, 6, 4}, /* Tx0 = Analog + S/PDIF. */
13 {8, 4, 0}, /* Tx1 = ADAT1. */
18 {10, 10, 4}, /* Tx0 = Analog + S/PDIF. */
19 {16, 4, 0}, /* Tx1 = ADAT1 + ADAT2 (available at low rate). */
31 if (err < 0) in snd_dice_detect_alesis_formats()
36 memcpy(dice->tx_pcm_chs, alesis_io14_tx_pcm_chs, in snd_dice_detect_alesis_formats()
40 memcpy(dice->tx_pcm_chs, alesis_io26_tx_pcm_chs, in snd_dice_detect_alesis_formats()
45 for (i = 0; i < SND_DICE_RATE_MODE_COUNT; ++i) in snd_dice_detect_alesis_formats()
[all …]
/kernel/linux/linux-5.10/sound/firewire/dice/
Ddice-alesis.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-alesis.c - a part of driver for DICE based devices
12 {6, 6, 4}, /* Tx0 = Analog + S/PDIF. */
13 {8, 4, 0}, /* Tx1 = ADAT1. */
18 {10, 10, 4}, /* Tx0 = Analog + S/PDIF. */
19 {16, 4, 0}, /* Tx1 = ADAT1 + ADAT2 (available at low rate). */
31 if (err < 0) in snd_dice_detect_alesis_formats()
36 memcpy(dice->tx_pcm_chs, alesis_io14_tx_pcm_chs, in snd_dice_detect_alesis_formats()
40 memcpy(dice->tx_pcm_chs, alesis_io26_tx_pcm_chs, in snd_dice_detect_alesis_formats()
45 for (i = 0; i < SND_DICE_RATE_MODE_COUNT; ++i) in snd_dice_detect_alesis_formats()
[all …]
/kernel/linux/linux-5.10/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4114_REG_PWRDN 0x00 /* power down */
12 #define AK4114_REG_FORMAT 0x01 /* format control */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
17 #define AK4114_REG_RCS0 0x06 /* receiver status 0 */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
[all …]
/kernel/linux/linux-6.6/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4114_REG_PWRDN 0x00 /* power down */
12 #define AK4114_REG_FORMAT 0x01 /* format control */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
17 #define AK4114_REG_RCS0 0x06 /* receiver status 0 */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
14 #define s0 0
22 3-way twofish
43 #define CD0 0x0(%rsp)
44 #define CD1 0x8(%rsp)
45 #define CD2 0x10(%rsp)
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
[all …]
/kernel/linux/linux-6.6/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
14 #define s0 0
22 3-way twofish
43 #define CD0 0x0(%rsp)
44 #define CD1 0x8(%rsp)
45 #define CD2 0x10(%rsp)
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
35 Channel 0 must be "tx0" or "rx0".
41 mboxes = <&lsio_mu1 0 0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
22 an internal Communications Port Programming Interface (CPPI5) (Host port 0).
23 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
25 Peripheral Root Complex (UDMA-P) controller.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Domap-spi.txt4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
28 #address-cells = <1>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
23 - qcom,sc8280xp-edp-phy
27 - description: PHY base register block
[all …]
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
14 const: 0
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
14 const: 0
18 - samsung,exynos7-ufs-phy
23 reg-names:
25 - const: phy-pma
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
57 - desc-sg[i]: i-th descriptor, transferring the i-th sg
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
57 - desc-sg[i]: i-th descriptor, transferring the i-th sg
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
[all …]

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