Searched +full:uc +full:- +full:bias +full:- +full:en (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Antoniu Miclaus <antoniu.miclaus@analog.com>16 https://www.analog.com/en/products/adrf6780.html21 - adi,adrf678026 spi-max-frequency:34 clock-names:36 - const: lo_in38 clock-output-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only97 st->data[0] = 0x80 | (reg << 1); in __adrf6780_spi_read()98 st->data[1] = 0x0; in __adrf6780_spi_read()99 st->data[2] = 0x0; in __adrf6780_spi_read()101 t.rx_buf = &st->data[0]; in __adrf6780_spi_read()102 t.tx_buf = &st->data[0]; in __adrf6780_spi_read()105 ret = spi_sync_transfer(st->spi, &t, 1); in __adrf6780_spi_read()109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); in __adrf6780_spi_read()119 mutex_lock(&st->lock); in adrf6780_spi_read()121 mutex_unlock(&st->lock); in adrf6780_spi_read()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */9 /* N-PHY registers. */18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */200 #define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */417 #define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */418 #define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */[all …]
7 Change-Id: I2f6375e746087a874cbea0a4240e92abfded33589 diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig12 --- /dev/null14 @@ -0,0 +1,38 @@34 +source "drivers/mxc/gpu-viv/Kconfig"53 diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile56 --- /dev/null58 @@ -0,0 +1,10 @@59 +obj-$(CONFIG_MXC_GPU_VIV) += gpu-viv/60 +obj-$(CONFIG_MXC_SIM) += sim/[all …]