Searched full:uhs (Results 1 – 25 of 334) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | socionext,uniphier-sd.yaml | 58 socionext,syscon-uhs-mode:
62 - description: phandle to syscon that configures UHS mode
65 A phandle to syscon with one argument that configures UHS mode.
104 pinctrl-names = "default", "uhs";
114 sd-uhs-sdr12;
115 sd-uhs-sdr25;
116 sd-uhs-sdr50;
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| D | cdns,sdhci.yaml | 51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
57 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the input path for SD UHS SDR25 timing
63 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the input path for SD UHS SDR50 timing
69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
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| D | sdhci-sprd.txt | 24 - pinctrl-1: should contain uhs mode pin control
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
60 sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
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| D | sdhci-st.txt | 51 - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
54 - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
107 sd-uhs-sdr50;
108 sd-uhs-sdr104;
109 sd-uhs-ddr50;
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| D | mmc-controller.yaml | 140 sd-uhs-sdr12:
143 SD UHS SDR12 speed is supported.
145 sd-uhs-sdr25:
148 SD UHS SDR25 speed is supported.
150 sd-uhs-sdr50:
153 SD UHS SDR50 speed is supported.
155 sd-uhs-sdr104:
158 SD UHS SDR104 speed is supported.
160 sd-uhs-ddr50:
163 SD UHS DDR50 speed is supported.
[all …]
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| D | sdhci-am654.yaml | 80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
150 description: Input tap delay for SD UHS SDR12 timing
156 description: Input tap delay for SD UHS SDR25 timing
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 49 cdns,phy-input-delay-sd-uhs-sdr12:
50 description: Value of the delay in the input path for SD UHS SDR12 timing
55 cdns,phy-input-delay-sd-uhs-sdr25:
56 description: Value of the delay in the input path for SD UHS SDR25 timing
61 cdns,phy-input-delay-sd-uhs-sdr50:
62 description: Value of the delay in the input path for SD UHS SDR50 timing
67 cdns,phy-input-delay-sd-uhs-ddr50:
68 description: Value of the delay in the input path for SD UHS DDR50 timing
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| D | sdhci-sprd.txt | 24 - pinctrl-1: should contain uhs mode pin control
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
60 sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
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| D | sdhci-st.txt | 51 - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
54 - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
107 sd-uhs-sdr50;
108 sd-uhs-sdr104;
109 sd-uhs-ddr50;
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| D | brcm,sdhci-brcmstb.txt | 6 NOTE: The driver disables all UHS speed modes by default and depends
21 sd-uhs-sdr50;
22 sd-uhs-ddr50;
23 sd-uhs-sdr104;
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| D | mmc-controller.yaml | 131 sd-uhs-sdr12:
134 SD UHS SDR12 speed is supported.
136 sd-uhs-sdr25:
139 SD UHS SDR25 speed is supported.
141 sd-uhs-sdr50:
144 SD UHS SDR50 speed is supported.
146 sd-uhs-sdr104:
149 SD UHS SDR104 speed is supported.
151 sd-uhs-ddr50:
154 SD UHS DDR50 speed is supported.
[all …]
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| D | socionext,uniphier-sd.yaml | 88 pinctrl-names = "default", "uhs";
98 sd-uhs-sdr12;
99 sd-uhs-sdr25;
100 sd-uhs-sdr50;
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| D | sdhci-am654.yaml | 70 description: Output tap delay for SD UHS SDR12 timing
76 description: Output tap delay for SD UHS SDR25 timing
82 description: Output tap delay for SD UHS SDR50 timing
88 description: Output tap delay for SD UHS SDR104 timing
94 description: Output tap delay for SD UHS DDR50 timing
140 description: Input tap delay for SD UHS SDR12 timing
146 description: Input tap delay for SD UHS SDR25 timing
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-clearfog-itx.dtsi | 28 sd-uhs-sdr104;
29 sd-uhs-sdr50;
30 sd-uhs-sdr25;
31 sd-uhs-sdr12;
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| D | fsl-ls1012a-rdb.dts | 22 sd-uhs-sdr104;
23 sd-uhs-sdr50;
24 sd-uhs-sdr25;
25 sd-uhs-sdr12;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6qdl-colibri-v1_1-uhs.dtsi | 40 sd-uhs-sdr12;
41 sd-uhs-sdr25;
42 sd-uhs-sdr50;
43 sd-uhs-sdr104;
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| D | rk3288-veyron-sdmmc.dtsi | 83 sd-uhs-sdr12;
84 sd-uhs-sdr25;
85 sd-uhs-sdr50;
86 sd-uhs-sdr104;
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| D | stih410-b2120.dts | 32 sd-uhs-sdr50;
33 sd-uhs-sdr104;
34 sd-uhs-ddr50;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/ |
| D | ums512-1h10.dts | 45 sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
46 sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>;
49 sd-uhs-sdr104;
50 sd-uhs-sdr50;
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| /kernel/linux/linux-6.6/arch/riscv/boot/dts/microchip/ |
| D | mpfs-polarberry.dts | 75 sd-uhs-sdr12;
76 sd-uhs-sdr25;
77 sd-uhs-sdr50;
78 sd-uhs-sdr104;
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| D | mpfs-sev-kit.dts | 108 sd-uhs-sdr12;
109 sd-uhs-sdr25;
110 sd-uhs-sdr50;
111 sd-uhs-sdr104;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1012a-rdb.dts | 29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
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| D | fsl-lx2160a-clearfog-itx.dtsi | 92 sd-uhs-sdr104;
93 sd-uhs-sdr50;
94 sd-uhs-sdr25;
95 sd-uhs-sdr12;
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/rockchip/ |
| D | rk3288-veyron-sdmmc.dtsi | 89 sd-uhs-sdr12;
90 sd-uhs-sdr25;
91 sd-uhs-sdr50;
92 sd-uhs-sdr104;
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | stih410-b2120.dts | 39 sd-uhs-sdr50;
40 sd-uhs-sdr104;
41 sd-uhs-ddr50;
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