Searched full:unified (Results 1 – 25 of 971) sorted by relevance
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
123 "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
129 "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
135 "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
141 "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
411 "PublicDescription": "Attributable Level 3 data or unified cache access, read",
414 "BriefDescription": "Attributable Level 3 data or unified cache access, read"
417 "PublicDescription": "Attributable Level 3 data or unified cache access, write",
420 "BriefDescription": "Attributable Level 3 data or unified cache access, write"
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ |
| D | recommended.json | 69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
123 "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
129 "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
135 "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
141 "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
411 "PublicDescription": "Attributable Level 3 data or unified cache access, read",
414 "BriefDescription": "Attributable Level 3 data or unified cache access, read"
417 "PublicDescription": "Attributable Level 3 data or unified cache access, write",
420 "BriefDescription": "Attributable Level 3 data or unified cache access, write"
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | l2_cache.json | 4 …"PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and…
8 …": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data an…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …evel 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data an…
28 …due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data an…
32 …ue to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data an…
48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
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| D | metrics.json | 157 …unified cache that stores both data and instruction. Note that cache accesses in this cache are ei…
164 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this…
171 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve…
178 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | l2_cache.json | 4 …"PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and…
8 …": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data an…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …evel 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data an…
28 …due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data an…
32 …ue to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data an…
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| D | metrics.json | 145 …unified cache that stores both data and instruction. Note that cache accesses in this cache are ei…
152 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this…
159 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve…
166 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 87 …"PublicDescription": "Attributable Level 3 unified cache refill. This event counts for any cacheab…
90 "BriefDescription": "Attributable Level 3 unified cache refill."
93 …"PublicDescription": "Attributable Level 3 unified cache access. This event counts for any cacheab…
96 "BriefDescription": "Attributable Level 3 unified cache access."
99 …"PublicDescription": "Attributable L2 data or unified TLB refill. This event counts on anyrefill o…
102 "BriefDescription": "Attributable L2 data or unified TLB refill"
105 …"PublicDescription": "Attributable L2 data or unified TLB access. This event counts on any access …
108 "BriefDescription": "Attributable L2 data or unified TLB access"
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| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| D | unified.h | 3 * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
12 .syntax unified
14 __asm__(".syntax unified");
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | unified.h | 3 * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
12 .syntax unified
14 __asm__(".syntax unified");
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| /kernel/linux/linux-6.6/drivers/accel/habanalabs/common/ |
| D | memory_mgr.c | 14 * @mmg: parent unified memory manager
106 * @mmg: parent unified memory manager
139 * @mmg: parent unified memory manager
224 * @mmg: unified memory manager
307 * hl_mem_mgr_init - initialize unified memory manager
312 * Initialize an instance of unified memory manager
322 * hl_mem_mgr_fini - release unified memory manager
324 * @mmg: parent unified memory manager
326 * Release the unified memory manager. Shall be called from an interrupt context.
348 * @mmg: parent unified memory manager
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 36 cache-unified: true
59 - cache-unified
72 cache-unified;
85 cache-unified;
97 cache-unified;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | socionext,uniphier-system-cache.yaml | 35 cache-unified: true
58 - cache-unified
71 cache-unified;
84 cache-unified;
96 cache-unified;
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| D | andestech,ax45mp-cache.yaml | 52 cache-unified: true
66 - cache-unified
80 cache-unified;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 225 cache-unified;
230 cache-unified;
246 cache-unified;
262 cache-unified;
278 cache-unified;
294 cache-unified;
310 cache-unified;
326 cache-unified;
342 cache-unified;
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| /kernel/linux/common_modules/ucollection/ |
| D | unified_collection_driver.c | 71 pr_err("failed to register unified collection device"); in unified_collection_init()
75 pr_info("register unified collection device successful"); in unified_collection_init()
81 pr_info("deregister unified collection device successful"); in unified_collection_exit()
89 MODULE_DESCRIPTION("Unified Collection Driver");
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| D | Kconfig | 4 tristate "Enable unified collection"
6 unified collection
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 18 - cache-unified : Specifies the cache is a unified cache.
26 cache-unified;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | sm4450.dtsi | 48 cache-unified;
54 cache-unified;
72 cache-unified;
90 cache-unified;
108 cache-unified;
126 cache-unified;
144 cache-unified;
162 cache-unified;
180 cache-unified;
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z13/ |
| D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z196/ |
| D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z10/ |
| D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-cpus.dtsi | 169 cache-unified;
177 cache-unified;
185 cache-unified;
193 cache-unified;
202 cache-unified;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.yaml | 52 cache-unified: true
78 - cache-unified
90 cache-unified;
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | m53xxacr.h | 17 * cache setup. They have a unified instruction and data cache, with
56 #define CACHE_SIZE 0x2000 /* 8k of unified cache */
60 #define CACHE_SIZE 0x4000 /* 16k of unified cache */
87 * Unified cache means we will never need to flush for coherency of
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