| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | marvell,armada-3700-utmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Miquel Raynal <miquel.raynal@bootlin.com>
14 On Armada 3700, there are two USB controllers, one is compatible with
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
24 reg:
27 "#phy-cells":
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| D | dm816x-phy.txt | 1 Device tree binding documentation for am816x USB PHY
5 - compatible : should be "ti,dm816x-usb-phy"
6 - reg : offset and length of the PHY register set.
7 - reg-names : name for the phy registers
8 - clocks : phandle to the clock
9 - clock-names : name of the clock
10 - syscon: phandle for the syscon node to access misc registers
11 - #phy-cells : from the generic PHY bindings, must be 1
12 - syscon: phandle for the syscon node to access misc registers
16 usb_phy0: usb-phy@20 {
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| D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
39 u2 port0 0x0000 MISC
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| D | mediatek,xsphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
20 u2 port0 0x0000 MISC
23 u2 port1 0x1000 MISC
26 u2 port2 0x2000 MISC
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/extcon/ |
| D | qcom,pm8941-misc.txt | 1 Qualcomm's PM8941 USB ID Extcon device
3 Some Qualcomm PMICs have a "misc" module that can be used to detect when
4 the USB ID pin has been pulled low or high.
8 - compatible:
11 Definition: Should contain "qcom,pm8941-misc";
13 - reg:
16 Definition: Should contain the offset to the misc address space
18 - interrupts:
20 Value type: <prop-encoded-array>
21 Definition: Should contain the usb id interrupt
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/extcon/ |
| D | qcom,pm8941-misc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/extcon/qcom,pm8941-misc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. PM8941 USB ID Extcon device
10 - Guru Das Srinagesh <quic_gurus@quicinc.com>
13 Some Qualcomm PMICs have a "misc" module that can be used to detect when
14 the USB ID pin has been pulled low or high.
19 - const: qcom,pm8941-misc
21 reg:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-mvebu-utmi.txt | 2 --------------------
7 On Armada 3700, there are two USB controllers, one is compatible with the USB2
14 - compatible: Should be one of:
15 * "marvell,a3700-utmi-host-phy" for the PHY connected to
16 the USB2 host-only controller.
17 * "marvell,a3700-utmi-otg-phy" for the PHY connected to
19 - reg: PHY IP register range.
20 - marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
23 - #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
29 compatible = "marvell,armada-3700-utmi-host-phy";
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| D | dm816x-phy.txt | 1 Device tree binding documentation for am816x USB PHY
5 - compatible : should be "ti,dm816x-usb-phy"
6 - reg : offset and length of the PHY register set.
7 - reg-names : name for the phy registers
8 - clocks : phandle to the clock
9 - clock-names : name of the clock
10 - syscon: phandle for the syscon node to access misc registers
11 - #phy-cells : from the generic PHY bindings, must be 1
12 - syscon: phandle for the syscon node to access misc registers
16 usb_phy0: usb-phy@20 {
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| D | phy-mtk-tphy.txt | 1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
[all …]
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| D | phy-mtk-xsphy.txt | 1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nspire/ |
| D | nspire.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
18 reg = <0>;
23 reg = <0x00000000 0x80000>;
27 compatible = "mmio-sram";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-37xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/ |
| D | armada-37xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
34 psci-area@4000000 {
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | nspire.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&intc>;
15 compatible = "arm,arm926ej-s";
20 reg = <0x00000000 0x80000>;
25 reg = <0xA4000000 0x20000>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <32768>;
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| D | qcom-pm8941.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/spmi/spmi.h>
9 compatible = "qcom,pm8941", "qcom,spmi-pmic";
10 reg = <0x0 SPMI_USID>;
11 #address-cells = <1>;
12 #size-cells = <0>;
15 compatible = "qcom,pm8941-rtc";
16 reg = <0x6000>,
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| D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
20 reg = <0>;
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
18 reg = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
18 reg = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/ |
| D | ge-achc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
5 ---
6 $id: http://devicetree.org/schemas/misc/ge-achc.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: GE Healthcare USB Management Controller
12 A device which handles data acquisition from compatible USB based peripherals.
15 Note: This device does not expose the peripherals as USB devices.
18 - Sebastian Reichel <sre@kernel.org>
23 - const: ge,achc
24 - const: nxp,kinetis-k20
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| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-utmi.c | 1 // SPDX-License-Identifier: GPL-2.0
48 /* Armada 3700 USB miscellaneous registers */
59 * struct mvebu_a3700_utmi_caps - PHY capabilities
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
72 * struct mvebu_a3700_utmi - PHY driver data
75 * @usb_misc: Regmap with USB miscellaneous registers including PHY ones
89 struct device *dev = &phy->dev; in mvebu_a3700_utmi_phy_power_on()
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
92 u32 reg; in mvebu_a3700_utmi_phy_power_on() local
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-utmi.c | 1 // SPDX-License-Identifier: GPL-2.0
48 /* Armada 3700 USB miscellaneous registers */
59 * struct mvebu_a3700_utmi_caps - PHY capabilities
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
72 * struct mvebu_a3700_utmi - PHY driver data
75 * @usb_misc: Regmap with USB miscellaneous registers including PHY ones
89 struct device *dev = &phy->dev; in mvebu_a3700_utmi_phy_power_on()
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
92 u32 reg; in mvebu_a3700_utmi_phy_power_on() local
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
20 reg = <0>;
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/bcmbca/ |
| D | bcm4908.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
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| /kernel/linux/linux-5.10/drivers/usb/host/ |
| D | bcma-hcd.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Broadcom USB-core driver (BCMA bus glue)
6 * Copyright 2011-2015 Hauke Mehrtens <hauke@hauke-m.de>
9 * Based on ssb-ohci driver
12 * Derived from the OHCI-PCI driver
14 * Copyright 2000-2002 David Brownell
18 * Derived from the USBcore related parts of Broadcom-SB
19 * Copyright 2005-2011 Broadcom Corporation
30 #include <linux/usb/ehci_pdriver.h>
31 #include <linux/usb/ohci_pdriver.h>
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| /kernel/linux/linux-6.6/drivers/usb/host/ |
| D | bcma-hcd.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Broadcom USB-core driver (BCMA bus glue)
6 * Copyright 2011-2015 Hauke Mehrtens <hauke@hauke-m.de>
9 * Based on ssb-ohci driver
12 * Derived from the OHCI-PCI driver
14 * Copyright 2000-2002 David Brownell
18 * Derived from the USBcore related parts of Broadcom-SB
19 * Copyright 2005-2011 Broadcom Corporation
30 #include <linux/usb/ehci_pdriver.h>
31 #include <linux/usb/ohci_pdriver.h>
[all …]
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