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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
5 usb {
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
12 * Internally, USB bus to the interconnect can only address up
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
5 usb {
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
12 * Internally, USB bus to the interconnect can only address up
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
[all …]
Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
[all …]
Darmada-385-db-ap.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
[all …]
Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
30 internal-regs {
35 clock-frequency = <600000000>;
40 compatible = "gpio-leds";
[all …]
Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
Darmada-385-db-ap.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
[all …]
Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/gemini/
Dgemini-wbd222.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Wiliboard WBD-222
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
12 model = "Wiliboard WBD-222";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/xilinx/
Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Konstantin Porotchkin <kostap@marvell.com>
14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
19 UTMI PHY0 --------/
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
[all …]
Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
66 label = "NOR Vitesse-7385 Firmware";
67 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
[all …]
Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
66 label = "NOR Vitesse-7385 Firmware";
67 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
27 * USB3.0 from the USB Complex and enable the PCIe controller.
37 &usb {
39 phy-names = "usb2-phy0", "usb2-phy1";
Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
27 * USB3.0 from the USB Complex and enable the PCIe controller.
37 &usb {
39 phy-names = "usb2-phy0", "usb2-phy1";
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
27 * USB3.0 from the USB Complex and enable the PCIe controller.
37 &usb {
39 phy-names = "usb2-phy0", "usb2-phy1";
Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
27 * USB3.0 from the USB Complex and enable the PCIe controller.
37 &usb {
39 phy-names = "usb2-phy0", "usb2-phy1";

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