| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | cdns,usb3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
14 const: cdns,usb3
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
[all …]
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| D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
23 connected to the Glue to serve as OTG ID change detection.
[all …]
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| D | ti,j721e-usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
10 - Roger Quadros <rogerq@ti.com>
15 - const: ti,j721e-usb
20 power-domains:
24 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
31 clock-names:
[all …]
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| D | generic.txt | 4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed-plus",
6 "super-speed", "high-speed", "full-speed" and
7 "low-speed". In case this isn't passed via DT, USB
10 - dr_mode: tells Dual-Role USB controllers that we want to work on a
12 "peripheral" and "otg". In case this attribute isn't
14 OTG.
15 - phy_type: tells USB controllers that we want to configure the core to support
16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
20 - otg-rev: tells usb driver the release number of the OTG and EH supplement
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | cdns,usb3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
14 const: cdns,usb3
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
[all …]
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| D | fsl,imx8qm-cdns3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Frank Li <Frank.Li@nxp.com>
15 const: fsl,imx8qm-usb3
19 - description: Register set for iMX USB3 Platform Control
21 "#address-cells":
24 "#size-cells":
31 - description: Standby clock. Used during ultra low power states.
[all …]
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| D | rockchip,rk3399-dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
28 - description:
[all …]
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| D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
23 connected to the Glue to serve as OTG ID change detection.
[all …]
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| D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 DRD Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
[all …]
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| D | starfive,jh7110-usb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
[all …]
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| D | ti,j721e-usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI wrapper module for the Cadence USBSS-DRD controller
10 - Roger Quadros <rogerq@kernel.org>
15 - const: ti,j721e-usb
16 - const: ti,am64-usb
17 - items:
18 - const: ti,j721e-usb
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
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| D | phy-mvebu-utmi.txt | 2 --------------------
8 and USB3 specifications and supports OTG. The other one is USB2 compliant and
14 - compatible: Should be one of:
15 * "marvell,a3700-utmi-host-phy" for the PHY connected to
16 the USB2 host-only controller.
17 * "marvell,a3700-utmi-otg-phy" for the PHY connected to
18 the USB3 and USB2 OTG capable controller.
19 - reg: PHY IP register range.
20 - marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
23 - #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
[all …]
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| D | allwinner,sun50i-h6-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun50i-h6-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/cdns3/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
11 #include <linux/usb/otg.h>
20 * struct cdns3_role_driver - host/gadget role driver
50 * struct cdns3 - Representation of Cadence USB3 DRD controller.
55 * @otg_res: the resource for otg
56 * @otg_v0_regs: pointer to base of v0 otg registers
57 * @otg_v1_regs: pointer to base of v1 otg registers
58 * @otg_cdnsp_regs: pointer to base of CDNSP otg registers
[all …]
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| /kernel/linux/linux-6.6/drivers/usb/cdns3/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
14 #include <linux/usb/otg.h>
20 * struct cdns_role_driver - host/gadget role driver
51 * struct cdns - Representation of Cadence USB3 DRD controller.
56 * @otg_res: the resource for otg
57 * @otg_v0_regs: pointer to base of v0 otg registers
58 * @otg_v1_regs: pointer to base of v1 otg registers
59 * @otg_cdnsp_regs: pointer to base of CDNSP otg registers
[all …]
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| D | cdns3-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Cadence.
6 * Copyright (C) 2017-2018 NXP
23 #include "gadget-export.h"
30 ret = phy_power_on(cdns->usb2_phy); in set_phy_power_on()
34 ret = phy_power_on(cdns->usb3_phy); in set_phy_power_on()
36 phy_power_off(cdns->usb2_phy); in set_phy_power_on()
43 phy_power_off(cdns->usb3_phy); in set_phy_power_off()
44 phy_power_off(cdns->usb2_phy); in set_phy_power_off()
48 * cdns3_plat_probe - probe for cdns3 core device
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra124-xusb-padctl.txt | 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra124-xusb-padctl.txt | 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
|