| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | qcom,msm8996-qmp-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8996)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
[all …]
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| D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
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| D | socionext,uniphier-usb3ss-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
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| D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
[all …]
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| D | qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq9574-qmp-usb3-phy
20 - qcom,qcm2290-qmp-usb3-phy
21 - qcom,sa8775p-qmp-usb3-uni-phy
[all …]
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| D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
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| D | bcm-ns-usb3-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 3.0 PHY
10 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
18 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,ns-ax-usb3-phy
24 - brcm,ns-bx-usb3-phy
30 usb3-dmp-syscon:
[all …]
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| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | amlogic,g12a-usb3-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-ns-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
56 struct phy *phy; member
58 int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value);
63 .compatible = "brcm,ns-ax-usb3-phy",
67 .compatible = "brcm,ns-bx-usb3-phy",
74 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, in bcm_ns_usb3_mdio_phy_write() argument
77 return usb3->phy_write(usb3, reg, value); in bcm_ns_usb3_mdio_phy_write()
80 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/broadcom/ |
| D | phy-bcm-ns-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
53 struct phy *phy; member
58 .compatible = "brcm,ns-ax-usb3-phy",
62 .compatible = "brcm,ns-bx-usb3-phy",
68 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
71 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
75 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
76 err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, in bcm_ns_usb3_phy_init_ns_bx()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
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| D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
34 --------------------
[all …]
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| D | socionext,uniphier-usb3ss-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
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| D | qcom,qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
[all …]
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| D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
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| D | bcm-ns-usb3-phy.txt | 1 Driver for Broadcom Northstar USB 3.0 PHY
5 - compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
6 - reg: address of MDIO bus device
7 - usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
9 - #phy-cells: must be 0
11 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
21 #size-cells = <1>;
22 #address-cells = <0>;
24 usb3-phy@10 {
25 compatible = "brcm,ns-ax-usb3-phy";
[all …]
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| D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/phy/phy.h>
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
149 /* USB 2.0 UTMI PHY support */
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-dwc3-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/socionext/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/socionext/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/ |
| D | tegra234-p3768-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "nvidia,p3768-0000";
11 stdout-path = "serial0:115200n8";
23 vcc-supply = <&vdd_1v8_sys>;
24 address-width = <8>;
27 read-only;
36 assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
37 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
47 usb2-0 {
52 usb2-1 {
[all …]
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