| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | maxlinear,gpy2xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Michael Walle <michael@walle.cc>
14 - $ref: ethernet-phy.yaml#
17 maxlinear,use-broken-interrupts:
19 Interrupts are broken on some GPY2xx PHYs in that they keep the
23 interrupts are disabled for this PHY and polling mode is used. If one
31 maxlinear,use-broken-interrupts: [ interrupts ]
[all …]
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| /kernel/linux/linux-6.6/arch/sh/ |
| D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
4 bool "Use LinuxSH standard BIOS"
6 Say Y here if your target has the gdb-sh-stub
8 in FLASH or EPROM. The kernel will use standard BIOS calls during
11 on-board Ethernet interface, and shut down the hardware). Note this
30 used by the SH-IPL bootloader, starting very early in the boot
37 bool "Use 4Kb for kernel stacks instead of 8Kb"
38 depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
40 If you say Y here the kernel will use a 4Kb stacksize for the
44 will also use IRQ stacks to compensate for the reduced stackspace.
[all …]
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| /kernel/linux/linux-5.10/arch/sh/ |
| D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
7 bool "Use LinuxSH standard BIOS"
9 Say Y here if your target has the gdb-sh-stub
11 in FLASH or EPROM. The kernel will use standard BIOS calls during
14 on-board Ethernet interface, and shut down the hardware). Note this
33 used by the SH-IPL bootloader, starting very early in the boot
40 bool "Use 4Kb for kernel stacks instead of 8Kb"
41 depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
43 If you say Y here the kernel will use a 4Kb stacksize for the
47 will also use IRQ stacks to compensate for the reduced stackspace.
[all …]
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| /kernel/linux/linux-6.6/arch/parisc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
79 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 The PA-RISC microprocessor is designed by Hewlett-Packard and used
92 and later HP3000 series). The PA-RISC Linux project home page is
152 # unless you want to implement ACPI on PA-RISC ... ;-)
168 depends on BROKEN
187 that can run on all 32-bit PA CPUs (albeit not optimally fast),
190 Specifying "PA8000" here will allow you to select a 64-bit kernel
196 Select this option for the PCX-L processor, as used in the
198 D200, D210, D300, D310 and E-class
[all …]
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| /kernel/linux/linux-5.10/arch/parisc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
64 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
72 The PA-RISC microprocessor is designed by Hewlett-Packard and used
74 and later HP3000 series). The PA-RISC Linux project home page is
88 default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT
89 default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT
122 # unless you want to implement ACPI on PA-RISC ... ;-)
134 depends on BROKEN
157 that can run on all 32-bit PA CPUs (albeit not optimally fast),
160 Specifying "PA8000" here will allow you to select a 64-bit kernel
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
27 reg-shift:
[all …]
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | cpwd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
6 * interface and Solaris-compatible ioctls as best it is
11 * timer interrupts. We use a timer to periodically
43 #define WD_BADMODEL "SUNW,501-5336"
82 bool broken; member
97 /* Sun uses Altera PLD EPF8820ATC144-4
100 * 1) RIC - sends an interrupt when triggered
101 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
102 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
[all …]
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | cpwd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
6 * interface and Solaris-compatible ioctls as best it is
11 * timer interrupts. We use a timer to periodically
43 #define WD_BADMODEL "SUNW,501-5336"
82 bool broken; member
97 /* Sun uses Altera PLD EPF8820ATC144-4
100 * 1) RIC - sends an interrupt when triggered
101 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
102 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
[all …]
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| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | pci_impl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * We can't just blindly use 64K for machines with EISA busses; they
15 * may also have PCI-PCI bridges present, and then we'd configure the
20 * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
31 * a single bit set. This is so that devices like the broken Myrinet card
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
44 * We accept the risk that a broken Myrinet card will be put into a true XL
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
58 * memory addresses. However, we do not use them all, in order to
[all …]
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| /kernel/linux/linux-6.6/arch/alpha/kernel/ |
| D | pci_impl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * We can't just blindly use 64K for machines with EISA busses; they
15 * may also have PCI-PCI bridges present, and then we'd configure the
20 * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
31 * a single bit set. This is so that devices like the broken Myrinet card
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
44 * We accept the risk that a broken Myrinet card will be put into a true XL
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
58 * memory addresses. However, we do not use them all, in order to
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | marvell,mv64xxx-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
15 - const: allwinner,sun4i-a10-i2c
16 - items:
17 - const: allwinner,sun7i-a20-i2c
18 - const: allwinner,sun4i-a10-i2c
19 - const: allwinner,sun6i-a31-i2c
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
24 - items:
[all …]
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| D | arm,arch_timer_mmio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/ |
| D | marvell,mv64xxx-i2c.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
15 - const: allwinner,sun4i-a10-i2c
16 - items:
17 - const: allwinner,sun7i-a20-i2c
18 - const: allwinner,sun4i-a10-i2c
19 - const: allwinner,sun6i-a31-i2c
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer_mmio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
[all …]
|
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
24 - items:
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | mpic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 * 0b00 = pass through (interrupts routed to IRQ0)
71 * Per-Processor registers
92 * Per-source registers
149 * Per-Processor registers
162 * Per-source registers
287 /* vector numbers used for FSL MPIC error interrupts */
355 /* Set this for a big-endian MPIC */
357 /* Broken U3 MPIC */
359 /* Broken IPI registers (autodetected) */
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | mpic.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 * 0b00 = pass through (interrupts routed to IRQ0)
71 * Per-Processor registers
92 * Per-source registers
149 * Per-Processor registers
162 * Per-source registers
287 /* vector numbers used for FSL MPIC error interrupts */
355 /* Set this for a big-endian MPIC */
357 /* Broken U3 MPIC */
359 /* Broken IPI registers (autodetected) */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/ |
| D | sun5i-a13-licheepi-one.dts | 4 * Based on sun5i-a13-olinuxino.dts, which is
5 * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
28 * restriction, including without limitation the rights to use,
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 /dts-v1/;
48 #include "sun5i-a13.dtsi"
49 #include "sunxi-common-regulators.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | sun5i-a13-licheepi-one.dts | 4 * Based on sun5i-a13-olinuxino.dts, which is
5 * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
28 * restriction, including without limitation the rights to use,
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 /dts-v1/;
48 #include "sun5i-a13.dtsi"
49 #include "sunxi-common-regulators.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
[all …]
|
| D | stm32746g-eval.dts | 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
24 * restriction, including without limitation the rights to use,
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 /dts-v1/;
45 #include "stm32f746-pinctrl.dtsi"
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
50 model = "STMicroelectronics STM32746g-EVAL board";
51 compatible = "st,stm32746g-eval", "st,stm32f746";
[all …]
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| /kernel/linux/linux-5.10/Documentation/networking/ |
| D | netdevices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 If device has registered successfully, it will be freed on last use
43 the MTU. A network device may use the MTU as mechanism to size receive
73 When the driver sets NETIF_F_LLTX in dev->features this will be
77 set_rx_mode. WARNING: use of NETIF_F_LLTX is deprecated.
78 Don't use it for new drivers.
81 will be called with interrupts disabled by netconsole.
87 Usually a bug, means queue start/stop flow control is broken in
101 napi->poll:
103 NAPI_STATE_SCHED bit in napi->state. Device
[all …]
|