| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/ |
| D | ingenic,adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
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| /kernel/linux/linux-5.10/drivers/hwmon/ |
| D | mlxreg-fan.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
34 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
35 * The logic in a programmable device measures the time t-high by sampling the
36 * tachometer every t-sample (with the default value 11.32 uS) and increment
38 * RPM = 15 / (t-sample * (K + Regval)), where:
40 * - 0xff - represents tachometer fault;
41 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
42 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
46 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
49 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
[all …]
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| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
|
| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
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| /kernel/linux/linux-6.6/drivers/hwmon/ |
| D | mlxreg-fan.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
15 etc. it is intended for use in applications where the counter
21 const: nxp,sysctr-timer
32 clock-names:
35 nxp,no-divider:
36 description: if present, means there is no internal base clk divider.
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/pl111/ |
| D | pl111_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
8 * Copyright (c) 2006-2008 Intel Corporation
16 #include <linux/clk-provider.h>
27 * CLCD Controller Internal Register addresses
104 * struct pl111_variant_data - encodes IP differences
110 * @broken_clockdivider: the clock divider is broken and we need to
111 * use the supplied clock directly
144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
146 /* pl111's internal clock divider. */
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/pl111/ |
| D | pl111_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
8 * Copyright (c) 2006-2008 Intel Corporation
16 #include <linux/clk-provider.h>
27 * CLCD Controller Internal Register addresses
104 * struct pl111_variant_data - encodes IP differences
110 * @broken_clockdivider: the clock divider is broken and we need to
111 * use the supplied clock directly
144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
146 /* pl111's internal clock divider. */
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
195 /* Input: Signal Type - to be converted to Encoder mode */
205 /* Output: If non-zero, this refDiv value should be used to calculate
208 /* Output: If non-zero, this postDiv value should be used to calculate
218 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
223 /* Calculated Reference divider of Display PLL */
225 /* Calculated Feedback divider of Display PLL */
227 /* Calculated Fractional Feedback divider of Display PLL */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
225 /* Calculated Reference divider of Display PLL */
227 /* Calculated Feedback divider of Display PLL */
229 /* Calculated Fractional Feedback divider of Display PLL */
[all …]
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| /kernel/linux/linux-5.10/drivers/iio/imu/inv_mpu6050/ |
| D | inv_mpu_aux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 TDK-InvenSense, Inc.
20 /* use 50hz frequency for xfer */ in inv_mpu_i2c_master_xfer()
29 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
34 user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; in inv_mpu_i2c_master_xfer()
35 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
39 /* wait for xfer: 1 period + half-period margin */ in inv_mpu_i2c_master_xfer()
43 user_ctrl = st->chip_config.user_ctrl; in inv_mpu_i2c_master_xfer()
44 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
49 d = st->chip_config.divider; in inv_mpu_i2c_master_xfer()
[all …]
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| D | inv_mpu_ring.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 * inv_mpu6050_update_period() - Update chip internal period estimation
33 (NSEC_PER_MSEC * (100 - INV_MPU6050_TS_PERIOD_JITTER)) / 100; in inv_mpu6050_update_period()
36 const s32 divider = INV_MPU6050_FREQ_DIVIDER(st); in inv_mpu6050_update_period() local
40 if (st->it_timestamp == 0) { in inv_mpu6050_update_period()
41 /* not initialized, forced to use it_timestamp */ in inv_mpu6050_update_period()
45 * Validate the use of it timestamp by checking if interrupt in inv_mpu6050_update_period()
51 delta = div_s64(timestamp - st->it_timestamp, divider); in inv_mpu6050_update_period()
53 /* update chip period and use it timestamp */ in inv_mpu6050_update_period()
54 st->chip_period = (st->chip_period + delta) / 2; in inv_mpu6050_update_period()
[all …]
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| /kernel/linux/linux-6.6/drivers/iio/imu/inv_mpu6050/ |
| D | inv_mpu_aux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 TDK-InvenSense, Inc.
20 /* use 50hz frequency for xfer */ in inv_mpu_i2c_master_xfer()
29 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
34 user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; in inv_mpu_i2c_master_xfer()
35 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
39 /* wait for xfer: 1 period + half-period margin */ in inv_mpu_i2c_master_xfer()
43 user_ctrl = st->chip_config.user_ctrl; in inv_mpu_i2c_master_xfer()
44 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
49 d = st->chip_config.divider; in inv_mpu_i2c_master_xfer()
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/platforms/512x/ |
| D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
39 /* extend the public set of clocks by adding internal slots for management */
65 /* internal, symbolic spec for the number of slots */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/512x/ |
| D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
39 /* extend the public set of clocks by adding internal slots for management */
65 /* internal, symbolic spec for the number of slots */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
[all …]
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | dw_mmc-starfive.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "dw_mmc-pltfm.h"
36 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
37 clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock; in dw_mci_starfive_set_ios()
38 ret = clk_set_rate(host->ciu_clk, clock); in dw_mci_starfive_set_ios()
40 dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock); in dw_mci_starfive_set_ios()
41 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_starfive_set_ios()
43 dev_dbg(host->dev, "Using the internal divider\n"); in dw_mci_starfive_set_ios()
51 struct dw_mci *host = slot->host; in dw_mci_starfive_execute_tuning()
52 struct starfive_priv *priv = host->priv; in dw_mci_starfive_execute_tuning()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
[all …]
|
| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
[all …]
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| /kernel/linux/linux-5.10/drivers/iio/adc/ |
| D | stm32-dfsdm-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
20 #include "stm32-dfsdm.h"
88 unsigned int spi_clk_out_div; /* SPI clkout divider value */
105 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
106 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
109 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable()
111 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable()
120 if (priv->aclk) in stm32_dfsdm_clk_disable_unprepare()
121 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r8a779a0-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/rcar-rst.h>
26 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
28 #include "renesas-cpg-mssr.h"
35 CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
36 CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
56 /* Internal Core Clocks */
98 /* Internal Core Clocks */
[all …]
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| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/dma/imx-dma.h>
26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
110 * According to RM, the divider range is 1 ~ 8,
114 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
115 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
116 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
[all …]
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| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-imx.h>
25 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
28 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
106 * According to RM, the divider range is 1 ~ 8,
110 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
111 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
112 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
113 4, 8, 16, 32, 64, 128, 256, 512, /* divider = 4 */
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
[all …]
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| /kernel/linux/linux-6.6/drivers/iio/adc/ |
| D | stm32-dfsdm-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
23 #include "stm32-dfsdm.h"
26 * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
113 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
114 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
117 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable()
119 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable()
128 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/ipu-v3/ |
| D | ipu-di.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
125 return readl(di->base + offset); in ipu_di_read()
130 writel(value, di->base + offset); in ipu_di_write()
166 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || in ipu_di_sync_config()
[all …]
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