| /kernel/linux/linux-5.10/drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 23 * vxge_vBIT(val, loc, sz) - set bits at offset
25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
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| /kernel/linux/linux-5.10/arch/alpha/lib/ |
| D | fpreg.c | 12 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
14 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
20 unsigned long val; in alpha_read_fp_reg() local
23 case 0: STT( 0, val); break; in alpha_read_fp_reg()
24 case 1: STT( 1, val); break; in alpha_read_fp_reg()
25 case 2: STT( 2, val); break; in alpha_read_fp_reg()
26 case 3: STT( 3, val); break; in alpha_read_fp_reg()
27 case 4: STT( 4, val); break; in alpha_read_fp_reg()
28 case 5: STT( 5, val); break; in alpha_read_fp_reg()
29 case 6: STT( 6, val); break; in alpha_read_fp_reg()
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| /kernel/linux/linux-6.6/arch/alpha/lib/ |
| D | fpreg.c | 14 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
16 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
22 unsigned long val; in alpha_read_fp_reg() local
28 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg()
30 case 0: STT( 0, val); break; in alpha_read_fp_reg()
31 case 1: STT( 1, val); break; in alpha_read_fp_reg()
32 case 2: STT( 2, val); break; in alpha_read_fp_reg()
33 case 3: STT( 3, val); break; in alpha_read_fp_reg()
34 case 4: STT( 4, val); break; in alpha_read_fp_reg()
35 case 5: STT( 5, val); break; in alpha_read_fp_reg()
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | arm.h | 41 UINT32 val; in OsArmReadSctlr() local
42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr()
43 return val; in OsArmReadSctlr()
46 STATIC INLINE VOID OsArmWriteSctlr(UINT32 val) in OsArmWriteSctlr() argument
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr()
54 UINT32 val; in OsArmReadActlr() local
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr()
56 return val; in OsArmReadActlr()
59 STATIC INLINE VOID OsArmWriteActlr(UINT32 val) in OsArmWriteActlr() argument
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr()
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| /kernel/linux/linux-6.6/arch/arm/include/asm/hardware/ |
| D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /kernel/linux/linux-6.6/drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /kernel/linux/linux-5.10/drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /kernel/linux/linux-5.10/drivers/media/tuners/ |
| D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /kernel/linux/linux-6.6/drivers/media/tuners/ |
| D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | adreno_pm4.xml.h | 475 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
477 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
483 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
489 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
493 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
495 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
503 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | a6xx.xml.h | 1021 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO() argument
1023 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MAS… in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1027 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI() argument
1029 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MAS… in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1033 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument
1035 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1039 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument
1041 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1047 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument
1049 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_ST… in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
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| D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
949 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| D | a5xx.xml.h | 1042 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1044 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1048 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1050 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1054 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE() argument
1056 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1060 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ() argument
1062 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; in A5XX_CP_PROTECT_REG_TRAP_READ()
1837 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB() argument
1839 …return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MA… in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
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| D | a4xx.xml.h | 844 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
846 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
901 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
903 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
907 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
909 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
923 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
925 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
929 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
931 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
| D | a6xx.xml.h | 1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START() argument
1125 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_ST… in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START()
1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START() argument
1131 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_ST… in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START()
1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument
1137 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument
1143 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument
1151 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_ST… in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
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| D | adreno_pm4.xml.h | 526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
528 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
534 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
540 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
546 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
554 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
949 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| D | a4xx.xml.h | 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
904 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
926 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| /kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/ |
| D | fw.h | 341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_IDX() argument
343 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_SEC_IDX()
346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_OFFSET() argument
348 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_SEC_OFFSET()
351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_LEN() argument
353 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_SEC_LEN()
356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_TYPE() argument
358 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); in RTW89_SET_FWCMD_SEC_TYPE()
361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_EXT_KEY() argument
363 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); in RTW89_SET_FWCMD_SEC_EXT_KEY()
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| /kernel/linux/linux-5.10/arch/loongarch/kvm/ |
| D | kvm_compat.h | 266 u32 val; in kvm_csr_readl() local
269 "csrrd %[val], %[reg] \n" in kvm_csr_readl()
270 : [val] "=r" (val) in kvm_csr_readl()
273 return val; in kvm_csr_readl()
278 u64 val; in kvm_csr_readq() local
281 "csrrd %[val], %[reg] \n" in kvm_csr_readq()
282 : [val] "=r" (val) in kvm_csr_readq()
285 return val; in kvm_csr_readq()
288 static inline void kvm_csr_writel(u32 val, u32 reg) in kvm_csr_writel() argument
291 "csrwr %[val], %[reg] \n" in kvm_csr_writel()
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| /kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /kernel/linux/linux-5.10/drivers/phy/ |
| D | phy-xgene.c | 554 u32 val; in sds_wr() local
564 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
565 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
567 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
576 u32 val; in sds_rd() local
584 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
585 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
588 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
597 u32 val; in cmu_wr() local
606 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /kernel/linux/linux-6.6/drivers/phy/ |
| D | phy-xgene.c | 555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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