| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.txt | 1 -----------------------------------------------------------------
2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
6 ZynqMP has an interface to communicate with secure firmware. Firmware
7 driver provides an interface to firmware APIs. Interface APIs can be
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
15 The clock controller is a hardware block of Xilinx versal clock tree. It
21 const: xlnx,versal-clk
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | xlnx,zynqmp-reset.txt | 1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
3 --------------------------------------------------------------------------
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,versal-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
14 using firmware interface.
19 - enum:
20 - xlnx,versal-fpga
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | versal-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
47 struct device *dev = &pdev->dev; in versal_fpga_probe()
51 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in versal_fpga_probe()
[all …]
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
88 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
92 present on the TS-73xx SBC boards.
128 safely handles AXI4MM and AXI4-Lite interfaces on a
161 Select this option to enable common support for Field-Programmable
210 the card. It also instantiates the SPI master (spi-altera) for
217 Select this option to enable PCIe driver for PCIe-based
218 Field-Programmable Gate Array (FPGA) solutions which implement
238 tristate "Xilinx Versal FPGA"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/ |
| D | xlnx,versal-net-cdx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 detect CDX bus and devices using the firmware.
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
34 - Nipun Gupta <nipun.gupta@amd.com>
[all …]
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| /kernel/linux/linux-6.6/drivers/reset/ |
| D | reset-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
13 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
107 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
[all …]
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| /kernel/linux/linux-5.10/drivers/reset/ |
| D | reset-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
14 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in zynqmp_reset_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/usb/dwc3/ |
| D | dwc3-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
35 /* Versal USB Reset ID */
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
74 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal()
79 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal()
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal()
[all …]
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| /kernel/linux/linux-6.6/drivers/firmware/xilinx/ |
| D | zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2022 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
27 #include <linux/firmware/xlnx-event-manager.h>
28 #include "zynqmp-debug.h"
35 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
37 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
43 /* Firmware feature check version mask */
[all …]
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| /kernel/linux/linux-5.10/drivers/firmware/xilinx/ |
| D | zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2021 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include "zynqmp-debug.h"
35 * struct pm_api_feature_data - PM API Feature data
53 * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
65 return -ENOTSUPP; in zynqmp_pm_ret_code()
67 return -EACCES; in zynqmp_pm_ret_code()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/zynqmp/ |
| D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
60 * struct zynqmp_clock - Clock
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
148 return -ENODEV; in zynqmp_is_valid_clock()
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
170 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/zynqmp/ |
| D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
61 * struct zynqmp_clock - Clock
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 return -ENODEV; in zynqmp_is_valid_clock()
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
171 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
[all …]
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-zynqmp-gqspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
149 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
[all …]
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| D | spi-cadence-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
304 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
311 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
[all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
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| /kernel/linux/linux-6.6/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/cadence/ |
| D | macb_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
57 * (bp)->rx_ring_size)
63 * (bp)->tx_ring_size)
66 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
77 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
[all …]
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch | 7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
45 obj-$(CONFIG_PHANTOM) += phantom.o
46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o
[all …]
|