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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/
Dxlnx,versal-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
19 - enum:
20 - xlnx,versal-fpga
23 - compatible
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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/kernel/linux/linux-6.6/drivers/fpga/
Dversal-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
47 struct device *dev = &pdev->dev; in versal_fpga_probe()
51 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in versal_fpga_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 The CDX bus manages multiple FPGA based hardware devices, which
14 devices. These FPGA based devices can be added/modified dynamically
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.txt1 -----------------------------------------------------------------
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
10 power management service, FPGA service and other platform management
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
19 - "smc" : SMC #0, following the SMCCC
20 - "hvc" : HVC #0, following the SMCCC
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/kernel/linux/linux-5.10/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
50 bool "Renesas R-Car Gen2 Internal PCI controller"
54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
56 built-in EHCI/OHCI host controller present on each one.
59 bool "Renesas R-Car PCIe controller"
64 Say Y here if you want PCIe controller support on R-Car SoCs.
68 bool "Renesas R-Car PCIe host controller"
73 Say Y here if you want PCIe controller support on R-Car SoCs in host
77 bool "Renesas R-Car PCIe endpoint controller"
81 Say Y here if you want PCIe controller support on R-Car SoCs in
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dxlnx,clocking-wizard.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
28 "#clock-cells":
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/kernel/linux/linux-6.6/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
22 FPGA.
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
115 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
149 in the Intel IXP4xx XScale-based network processor SoC.
185 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
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/kernel/linux/linux-6.6/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
27 #include <linux/firmware/xlnx-event-manager.h>
28 #include "zynqmp-debug.h"
35 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
37 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
64 * struct pm_api_feature_data - PM API Feature data
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/kernel/linux/linux-5.10/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2021 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include "zynqmp-debug.h"
35 * struct pm_api_feature_data - PM API Feature data
53 * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
65 return -ENOTSUPP; in zynqmp_pm_ret_code()
67 return -EACCES; in zynqmp_pm_ret_code()
69 return -ECANCELED; in zynqmp_pm_ret_code()
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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