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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
45 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
57 $ref: /schemas/clock/xlnx,versal-clk.yaml#
58 description: The clock controller is a hardware block of Xilinx versal
83 versal-firmware {
84 compatible = "xlnx,versal-firmware";
88 compatible = "xlnx,versal-fpga";
97 compatible = "xlnx,versal-clk";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/
Dxlnx,versal-fpga.yaml4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
30 compatible = "xlnx,versal-fpga";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
13 The clock controller is a hardware block of Xilinx versal clock tree. It
21 - xlnx,versal-clk
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
55 - xlnx,versal-clk
112 compatible = "xlnx,versal-clk";
Dxlnx,clocking-wizard.yaml13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
27 For list of all valid reset indices for Versal
28 <dt-bindings/reset/xlnx-versal-resets.h>
34 - xlnx,versal-reset
35 - xlnx,versal-net-reset
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
14 "xlnx,versal-reset" for Versal platform
43 For list of all valid reset indices for Versal see
44 <dt-bindings/reset/xlnx-versal-resets.h>
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dxlnx,versal-wwdt.yaml4 $id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
7 title: Xilinx Versal window watchdog timer controller
13 Versal watchdog intellectual property uses window watchdog mode.
27 - xlnx,versal-wwdt
45 compatible = "xlnx,versal-wwdt";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
15 The clock controller is a hardware block of Xilinx versal clock tree. It
21 const: xlnx,versal-clk
56 compatible = "xlnx,versal-clk";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dxilinx-versal-cpm.yaml4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
75 versal {
79 compatible = "xlnx,versal-cpm-host-1.00";
106 compatible = "xlnx,versal-cpm5-host";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.txt16 "xlnx,versal-firmware" for Versal
36 Versal
39 versal_firmware: versal-firmware {
40 compatible = "xlnx,versal-firmware";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dxilinx-versal-cpm.yaml4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
17 const: xlnx,versal-cpm-host-1.00
70 versal {
74 compatible = "xlnx,versal-cpm-host-1.00";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
61 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
238 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
/kernel/linux/linux-6.6/drivers/fpga/
Dversal-fpga.c57 mgr = devm_fpga_mgr_register(dev, "Xilinx Versal FPGA Manager", in versal_fpga_probe()
63 { .compatible = "xlnx,versal-fpga", },
79 MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
DKconfig238 tristate "Xilinx Versal FPGA"
242 Xilinx Versal SoC. This driver uses the firmware interface to
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dxlnx,versal-net-cdx.yaml4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
39 const: xlnx,versal-net-cdx
73 compatible = "xlnx,versal-net-cdx";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/
Dgpio-zynq.yaml17 - xlnx,versal-gpio-1.0
74 - xlnx,versal-gpio-1.0
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml29 - xlnx,versal-8.9a
60 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
225 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
/kernel/linux/linux-6.6/drivers/reset/
Dreset-zynqmp.c127 { .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
128 { .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, },
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml18 const: xlnx,versal-ospi-1.0
74 - xlnx,versal-ospi-1.0
Dspi-zynqmp-qspi.yaml18 - xlnx,versal-qspi-1.0
/kernel/linux/linux-6.6/drivers/cdx/controller/
Dcdx_controller.c3 * CDX host controller driver for AMD versal-net platform.
194 {.compatible = "xlnx,versal-net-cdx",},
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml30 - xlnx,versal-gem # Xilinx Versal
/kernel/linux/linux-5.10/drivers/pci/controller/
DKconfig106 bool "Xilinx Versal CPM host bridge support"
111 Xilinx Versal CPM host bridge.
/kernel/linux/linux-6.6/drivers/watchdog/
Dxilinx_wwdt.c3 * Window watchdog device driver for Xilinx Versal WWDT
236 { .compatible = "xlnx,versal-wwdt", },
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dgpio-zynq.txt10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0

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