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Searched full:vs2 (Results 1 – 12 of 12) sorted by relevance

/arkcompiler/runtime_core/static_core/tests/cts-assembly/
Darrays-02.pa21 # - sig: starr vs1, vs2
Darrays-04.pa31 # - sig: fstarr.32 vs1, vs2
Darrays-03.pa31 # - sig: fstarr.64 vs1, vs2
Darrays-06.pa30 # - sig: starr vs1, vs2
/arkcompiler/runtime_core/tests/cts-assembly/
Darrays-02.pa21 # - sig: starr vs1, vs2
Darrays-04.pa31 # - sig: fstarr.32 vs1, vs2
Darrays-03.pa31 # - sig: fstarr.64 vs1, vs2
Darrays-06.pa30 # - sig: starr vs1, vs2
/arkcompiler/runtime_core/static_core/isa/
Disa.yaml1625 acc = (vs1 + vs2) % 2^32
1627 acc = (vs1 - vs2) % 2^32
1629 acc = (vs1 * vs2) % 2^32
1631 acc = vs1 & vs2
1633 acc = vs1 | vs2
1635 acc = vs1 ^ vs2
1637 acc = (vs1 << (vs2 & 0x1f)) % 2^32
1639 acc = vs1 >> (vs2 & 0x1f)
1641 acc = (vs1 < 0) ? ~(~vs1 >> vs2 & 0x1f) : vs1 >> vs2 & 0x1f
1756 if vs2 == 0 then
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/arkcompiler/runtime_core/static_core/irtoc/scripts/
Dinterpreter.irt946 macro(:"handle_#{op.downcase}_v4_v4") do |vs1, vs2|
947 set_acc_primitive(send(op, vs1, vs2).i32).i32
1011 macro(:"handle_#{op.downcase}_v4_v4") do |vs1, vs2|
1012 If(vs2, 0).EQ.Unlikely {
1016 set_acc_primitive(send(op, vs1, vs2).i32)
1202 macro(:"handle_starr_#{size}_v4_v4") do |vs1, vs2|
1208 If(vs2, len_array).AE.Unlikely {
1209 call_runtime("ThrowArrayIndexOutOfBoundsExceptionFromInterpreter", vs2, len_array).void
1212 elem_offset = AddI(ShlI(vs2).Imm(elem_size_shift).u32).Imm(Constants::ARRAY_DATA_OFFSET).u32
1218 macro(:"handle_#{name}_v4_v4") do |vs1, vs2|
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/arkcompiler/runtime_core/static_core/verification/absint/
Dabs_int_inl.h1786 uint16_t vs2 = inst_.GetVReg<FORMAT, 0x01>(); in HandleInitobj() local
1790 std::array<int, 4UL> regs {vs1, vs2, vs3, vs4}; in HandleInitobj()
1800 uint16_t vs2 = inst_.GetVReg<FORMAT, 0x01>(); in HandleInitobjShort() local
1802 std::array<int, 2UL> regs {vs1, vs2}; in HandleInitobjShort()
3138 uint16_t vs2 = inst_.GetVReg<FORMAT, 0x01>(); in HandleCallShort() local
3151 std::array<int, 2UL> regs {vs1, vs2}; in HandleCallShort()
3204 uint16_t vs2 = inst_.GetVReg<FORMAT, 0x01>(); in HandleCall() local
3219 std::array<int, 4UL> regs {vs1, vs2, vs3, vs4}; in HandleCall()
3290 uint16_t vs2 = inst_.GetVReg<FORMAT, 0x01>(); in HandleCallVirtShort() local
3302 std::array<int, 2UL> regs {vs1, vs2}; in HandleCallVirtShort()
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/arkcompiler/runtime_core/static_core/runtime/interpreter/
Dinterpreter-inl.h2977 uint16_t vs2 = this->GetInst().template GetVReg<FORMAT, 1>(); in HandleArrayStore() local
2980 << "store v" << vs1 << ", v" << vs2; in HandleArrayStore()
2983 int32_t idx = this->GetFrame()->GetVReg(vs2).Get(); in HandleArrayStore()
3643 uint16_t vs2 = this->GetInst().template GetVReg<FORMAT, 1>(); in HandleBinaryOp() local
3646 << "binop2 v" << vs1 << ", v" << vs2; in HandleBinaryOp()
3649 OpT v2 = this->GetFrame()->GetVReg(vs2).template GetAs<OpT>(); in HandleBinaryOp()
3664 uint16_t vs2 = this->GetInst().template GetVReg<FORMAT, 1>(); in HandleBinaryOpV() local
3667 << "binop.v v" << vs1 << ", v" << vs2; in HandleBinaryOpV()
3670 OpT v2 = this->GetFrame()->GetVReg(vs2).template GetAs<OpT>(); in HandleBinaryOpV()