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/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
Drcar_du_plane.c86 * VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0 or
89 * Allocate the correct fixed plane when sourcing frames from VSPD0 or VSPD1,
111 /* VSPD1 feeds plane 1 on DU0/1 or plane 0 on DU2. */ in rcar_du_plane_hwalloc()
Drcar_du_group.c66 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for in rcar_du_group_setup_defr8()
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_du_plane.c85 * VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0 or
88 * Allocate the correct fixed plane when sourcing frames from VSPD0 or VSPD1,
110 /* VSPD1 feeds plane 1 on DU0/1 or plane 0 on DU2. */ in rcar_du_plane_hwalloc()
Drcar_du_group.c66 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for in rcar_du_group_setup_defr8()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Drenesas,du.txt116 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr8a7795-cpg-mssr.c199 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
383 { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
Dr8a77995-cpg-mssr.c147 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
Dr8a774c0-cpg-mssr.c176 DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
Dr8a77990-cpg-mssr.c181 DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
Dr8a774b1-cpg-mssr.c164 DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
Dr8a77965-cpg-mssr.c184 DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
Dr8a774a1-cpg-mssr.c169 DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
Dr8a774e1-cpg-mssr.c181 DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
Dr8a7796-cpg-mssr.c188 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a77950.dtsi33 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr8a77995-cpg-mssr.c159 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
Dr8a779a0-cpg-mssr.c221 DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
Dr8a774c0-cpg-mssr.c185 DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
Dr8a77990-cpg-mssr.c195 DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
Dr8a779g0-cpg-mssr.c228 DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
Dr8a774b1-cpg-mssr.c176 DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
Dr8a774a1-cpg-mssr.c181 DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
Dr8a77965-cpg-mssr.c194 DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
Dr8a774e1-cpg-mssr.c186 DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
Dr8a7796-cpg-mssr.c198 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),

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