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/kernel/linux/linux-6.6/Documentation/scheduler/
D	sched-stats.rst	11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel 43 1) # of times sched_yield() was called 49 3) # of times schedule() was called 54 5) # of times try_to_wake_up() was called 55 6) # of times try_to_wake_up() was called to wake up the local cpu 78 1) # of times in this domain load_balance() was called when the 79 cpu was idle 81 the load did not require balancing when the cpu was idle 83 more tasks and failed, when the cpu was idle 85 load_balance() in this domain when the cpu was idle [all …]
/kernel/linux/linux-5.10/Documentation/scheduler/
D	sched-stats.rst	11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel 43 1) # of times sched_yield() was called 49 3) # of times schedule() was called 54 5) # of times try_to_wake_up() was called 55 6) # of times try_to_wake_up() was called to wake up the local cpu 78 1) # of times in this domain load_balance() was called when the 79 cpu was idle 81 the load did not require balancing when the cpu was idle 83 more tasks and failed, when the cpu was idle 85 load_balance() in this domain when the cpu was idle [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	41 "BriefDescription": "Cycles when a demand ifetch was pending", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … [all …]
D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f… 30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 … [all …]
D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local… [all …]
D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum… 30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu… 36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch… 42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi… 59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,… 60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p… 65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	41 "BriefDescription": "Cycles when a demand ifetch was pending", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … [all …]
D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f… 30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 … [all …]
D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local… [all …]
D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum… 30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu… 36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch… 42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi… 59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,… 60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p… 65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power10/
D	pipeline.json	40 "BriefDescription": "The instruction was flushed after becoming next-to-complete (NTC)." 45 …"BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling… 50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 80 …-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR … 85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load… 90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the s… 95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t… 105 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l… 125 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power9/
D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i… 50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/
D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i… 50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	10 Soon after the V4L API was added to the kernel it was criticised as too 15 another four years and two stable kernel releases until the new API was 23 1998-08-27: The :c:func:`select()` function was introduced. 27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise 39 1998-10-02: The ``id`` field was removed from 41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was 45 Codec API was released. 50 1998-11-12: The read/write directon of some ioctls was misdefined. 57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from 58 ``videodev.h`` since it was only used once in the ``videodev`` kernel [all …]
/kernel/linux/linux-6.6/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	10 Soon after the V4L API was added to the kernel it was criticised as too 15 another four years and two stable kernel releases until the new API was 23 1998-08-27: The :c:func:`select()` function was introduced. 27 1998-09-18: The ``VIDIOC_NONCAP`` ioctl was replaced by the otherwise 39 1998-10-02: The ``id`` field was removed from 41 renamed. The :ref:`VIDIOC_QUERYSTD` ioctl was 45 Codec API was released. 50 1998-11-12: The read/write direction of some ioctls was misdefined. 57 with ``V4L2_CID_AUDIO``. The ``V4L2_MAJOR`` define was removed from 58 ``videodev.h`` since it was only used once in the ``videodev`` kernel [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z14/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …on Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for… 21 …s for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DT… 28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a … 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement… 56 …r the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the IT… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z15/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …on Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for… 21 …s for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DT… 28 …"PublicDescription": "A translation entry was written into the Combined Region and Segment Table E… 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement… 56 …r the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the IT… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 14 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca… 28 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a … 35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 49 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 70 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	13 …ritebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 149 …ad uops retired that hit in the L3 cache, in which a snoop was required and modified data was forw… 278 …ads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 287 … reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 296 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … 305 …": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop … 314 …: "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy t… 341 …hes that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 350 …etches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 359 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	13 …ritebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 149 …ad uops retired that hit in the L3 cache, in which a snoop was required and modified data was forw… 278 …ads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 287 … reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 296 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … 305 …": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop … 314 …: "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy t… 341 …hes that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 350 …etches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 359 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … [all …]
/kernel/linux/linux-5.10/arch/arm/tools/
D	syscall.tbl	`21 # 7 was sys_waitpid 31 # 17 was sys_break 32 # 18 was sys_stat 42 # 28 was sys_fstat 45 # 31 was sys_stty 46 # 32 was sys_gtty 49 # 35 was sys_ftime 58 # 44 was sys_prof 62 # 48 was sys_signal 67 # 53 was sys_lock [all …]`
/kernel/linux/linux-6.6/arch/arm/tools/
D	syscall.tbl	`21 # 7 was sys_waitpid 31 # 17 was sys_break 32 # 18 was sys_stat 42 # 28 was sys_fstat 45 # 31 was sys_stty 46 # 32 was sys_gtty 49 # 35 was sys_ftime 58 # 44 was sys_prof 62 # 48 was sys_signal 67 # 53 was sys_lock [all …]`
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 133 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 140 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 147 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 154 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… [all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/s390/cf_z13/
D	extended.json	7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 63 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 112 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 119 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 133 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 140 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 147 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 154 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… [all …]

12 3 4 5 6 7 8 9 10 >>...440