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/kernel/linux/linux-5.10/arch/mips/mm/
Dc-octeon.c181 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
184 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
185 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
191 c->dcache.ways = 64; in probe_octeon()
193 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
194 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; in probe_octeon()
201 c->icache.ways = 37; in probe_octeon()
203 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
206 c->dcache.ways = 32; in probe_octeon()
208 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
[all …]
Dc-r4k.c266 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
299 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32_page_indexed()
1121 c->icache.ways = 2; in probe_pcache()
1126 c->dcache.ways = 2; in probe_pcache()
1135 c->icache.ways = 2; in probe_pcache()
1140 c->dcache.ways = 2; in probe_pcache()
1149 c->icache.ways = 4; in probe_pcache()
1154 c->dcache.ways = 4; in probe_pcache()
1169 c->icache.ways = 1; in probe_pcache()
1174 c->dcache.ways = 1; in probe_pcache()
[all …]
Dc-tx39.c302 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
303 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
308 current_cpu_data.icache.ways = 2; in tx39_probe_cache()
309 current_cpu_data.dcache.ways = 2; in tx39_probe_cache()
315 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
316 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
383 (dcache_size / current_cpu_data.dcache.ways) - 1, in tx39_cache_init()
392 current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways; in tx39_cache_init()
393 current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways; in tx39_cache_init()
Dsc-mips.c170 c->scache.ways = assoc + 1; in mips_sc_probe_cm3()
220 c->scache.ways = tmp + 1; in mips_sc_probe()
227 * According to config2 it would be 5-ways, but that is in mips_sc_probe()
232 c->scache.ways = 4; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
242 c->scache.ways = 4; in mips_sc_probe()
/kernel/linux/linux-6.6/arch/mips/mm/
Dc-octeon.c184 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
188 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
194 c->dcache.ways = 64; in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
197 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; in probe_octeon()
204 c->icache.ways = 37; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
209 c->dcache.ways = 32; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
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Dc-r4k.c233 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
1010 c->icache.ways = 2; in probe_pcache()
1015 c->dcache.ways = 2; in probe_pcache()
1024 c->icache.ways = 2; in probe_pcache()
1029 c->dcache.ways = 2; in probe_pcache()
1038 c->icache.ways = 4; in probe_pcache()
1043 c->dcache.ways = 4; in probe_pcache()
1059 c->icache.ways = 1; in probe_pcache()
1064 c->dcache.ways = 1; in probe_pcache()
1076 c->icache.ways = 2; in probe_pcache()
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Dsc-mips.c170 c->scache.ways = assoc + 1; in mips_sc_probe_cm3()
220 c->scache.ways = tmp + 1; in mips_sc_probe()
227 * According to config2 it would be 5-ways, but that is in mips_sc_probe()
232 c->scache.ways = 4; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
242 c->scache.ways = 4; in mips_sc_probe()
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/
Dprobe.c38 boot_cpu_data.icache.ways = 1; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache.ways = 2; in cpu_probe()
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/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4/
Dprobe.c38 boot_cpu_data.icache.ways = 1; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
67 boot_cpu_data.icache.ways = 4; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
171 boot_cpu_data.icache.ways = 2; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
176 boot_cpu_data.icache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
192 boot_cpu_data.icache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache.ways = 2; in cpu_probe()
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
Dcache.json54 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
57 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
60 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
63 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
66 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
69 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm2836.dtsi58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
Dbcm2837.dtsi57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm2837.dtsi58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
73 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
76 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
88 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
91 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
103 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
106 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
/kernel/linux/linux-6.6/arch/sh/mm/
Dcache-sh7705.c33 unsigned long ways, waysize, addrstart; in cache_wback_all() local
35 ways = current_cpu_data.dcache.ways; in cache_wback_all()
58 } while (--ways); in cache_wback_all()
82 unsigned long ways, waysize, addrstart; in __flush_dcache_page() local
103 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
125 } while (--ways); in __flush_dcache_page()
/kernel/linux/linux-5.10/arch/sh/mm/
Dcache-sh7705.c32 unsigned long ways, waysize, addrstart; in cache_wback_all() local
34 ways = current_cpu_data.dcache.ways; in cache_wback_all()
57 } while (--ways); in cache_wback_all()
81 unsigned long ways, waysize, addrstart; in __flush_dcache_page() local
102 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
124 } while (--ways); in __flush_dcache_page()
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
Dcache.json111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
123 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
126 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/kernel/linux/linux-6.6/arch/mips/include/asm/octeon/
Dcvmx-l2c.h188 * the cache 'ways' that a core can evict from.
197 * @mask: The partitioning of the ways expressed as a binary
204 * @note If any ways are blocked for all cores and the HW blocks, then
205 * those ways will never have any cache lines evicted from them.
207 * ways regardless of the partitioning.
215 * the cache 'ways' that a core can evict from.
223 * @mask: The partitioning of the ways expressed as a binary
230 * @note If any ways are blocked for all cores and the HW blocks, then
231 * those ways will never have any cache lines evicted from them.
233 * ways regardless of the partitioning.
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-l2c.h188 * the cache 'ways' that a core can evict from.
197 * @mask: The partitioning of the ways expressed as a binary
204 * @note If any ways are blocked for all cores and the HW blocks, then
205 * those ways will never have any cache lines evicted from them.
207 * ways regardless of the partitioning.
215 * the cache 'ways' that a core can evict from.
223 * @mask: The partitioning of the ways expressed as a binary
230 * @note If any ways are blocked for all cores and the HW blocks, then
231 * those ways will never have any cache lines evicted from them.
233 * ways regardless of the partitioning.
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/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_npc_hash.c474 /* Check all the 4 ways for a free slot. */ in rvu_npc_exact_alloc_mem_table_entry()
476 for (i = 0; i < table->mem_table.ways; i++) { in rvu_npc_exact_alloc_mem_table_entry()
771 * @ways: MEM table ways.
784 static int rvu_npc_exact_add_to_list(struct rvu *rvu, enum npc_exact_opc_type opc_type, u8 ways, in rvu_npc_exact_add_to_list() argument
792 WARN_ON(ways >= NPC_EXACT_TBL_MAX_WAYS); in rvu_npc_exact_add_to_list()
814 lhead = &table->lhead_mem_tbl_entry[ways]; in rvu_npc_exact_add_to_list()
832 entry->ways = ways; in rvu_npc_exact_add_to_list()
868 * @ways: ways for MEM table.
872 static void rvu_npc_exact_mem_table_write(struct rvu *rvu, int blkaddr, u8 ways, in rvu_npc_exact_mem_table_write() argument
875 rvu_write64(rvu, blkaddr, NPC_AF_EXACT_MEM_ENTRY(ways, index), mdata); in rvu_npc_exact_mem_table_write()
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/kernel/linux/linux-5.10/arch/arc/mm/
Dtlb.c64 * map into same set, there would be contention for the 2 ways causing severe
68 * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
239 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
711 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8; in read_decode_mmu_bcr() member
713 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8; in read_decode_mmu_bcr()
719 unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, in read_decode_mmu_bcr() member
723 ways:4, ver:8; in read_decode_mmu_bcr()
746 mmu->ways = 1 << mmu2->ways; in read_decode_mmu_bcr()
753 mmu->ways = 1 << mmu3->ways; in read_decode_mmu_bcr()
763 mmu->ways = mmu4->n_ways * 2; in read_decode_mmu_bcr()
[all …]
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/
Dinit.c126 unsigned long ways, waysize, addrstart; in cache_init() local
144 ways = 1; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
159 } while (--ways); in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
200 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/
Dinit.c126 unsigned long ways, waysize, addrstart; in cache_init() local
144 ways = 1; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
159 } while (--ways); in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
200 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
/kernel/linux/linux-6.6/arch/arc/mm/
Dtlb.c22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
585 mmu->ways = 1 << mmu3->ways; in arc_mmu_mumbojumbo()
594 mmu->ways = mmu4->n_ways * 2; in arc_mmu_mumbojumbo()
609 mmu->sets, mmu->ways, in arc_mmu_mumbojumbo()
686 * However for walking WAYS of a SET, we need to know this
688 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
693 * time of lookup matching multiple ways.
705 int set, n_ways = mmu->ways; in do_tlb_overlap_fault()
708 BUG_ON(mmu->ways > 4); in do_tlb_overlap_fault()
[all …]
/kernel/linux/linux-5.10/arch/nds32/kernel/
Dsetup.c104 L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE); in dump_cpu_info()
108 L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size * in dump_cpu_info()
111 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, in dump_cpu_info()
113 L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE); in dump_cpu_info()
117 L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size * in dump_cpu_info()
120 L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways, in dump_cpu_info()
132 L1_cache_info[ICACHE].ways; in dump_cpu_info()
138 L1_cache_info[DCACHE].ways; in dump_cpu_info()
/kernel/linux/linux-5.10/drivers/soc/qcom/
Dllcc-qcom.c57 * @bonus_ways: Bonus ways are additional ways to be used for any slice,
58 * if client ends up using more than reserved cache ways. Bonus
59 * ways are allocated only if they are not reserved for some
61 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
65 * @probe_target_ways: Determines what ways to probe for access hit. When
66 * configured to 1 only bonus and reserved ways are probed.
67 * When configured to 0 all ways in llcc are probed.
70 * then the ways assigned to this client are not flushed on power

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