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/kernel/linux/linux-5.10/arch/hexagon/kernel/
Dvm_init_segtable.S40 #define X __HVM_PDE_S_INVALID macro
47 .word X,X,X,X
48 .word X,X,X,X
49 .word X,X,X,X
50 .word X,X,X,X
51 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
52 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
53 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
54 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
55 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
[all …]
/kernel/linux/linux-6.6/arch/hexagon/kernel/
Dvm_init_segtable.S40 #define X __HVM_PDE_S_INVALID macro
47 .word X,X,X,X
48 .word X,X,X,X
49 .word X,X,X,X
50 .word X,X,X,X
51 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
52 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
53 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
54 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
55 .word X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Dcrct10dif-vpmsum_asm.S21 /* x^261184 mod p(x), x^261120 mod p(x) */
24 /* x^260160 mod p(x), x^260096 mod p(x) */
27 /* x^259136 mod p(x), x^259072 mod p(x) */
30 /* x^258112 mod p(x), x^258048 mod p(x) */
33 /* x^257088 mod p(x), x^257024 mod p(x) */
36 /* x^256064 mod p(x), x^256000 mod p(x) */
39 /* x^255040 mod p(x), x^254976 mod p(x) */
42 /* x^254016 mod p(x), x^253952 mod p(x) */
45 /* x^252992 mod p(x), x^252928 mod p(x) */
48 /* x^251968 mod p(x), x^251904 mod p(x) */
[all …]
Dcrc32c-vpmsum_asm.S17 /* x^261120 mod p(x)` << 1, x^261184 mod p(x)` << 1 */
20 /* x^260096 mod p(x)` << 1, x^260160 mod p(x)` << 1 */
23 /* x^259072 mod p(x)` << 1, x^259136 mod p(x)` << 1 */
26 /* x^258048 mod p(x)` << 1, x^258112 mod p(x)` << 1 */
29 /* x^257024 mod p(x)` << 1, x^257088 mod p(x)` << 1 */
32 /* x^256000 mod p(x)` << 1, x^256064 mod p(x)` << 1 */
35 /* x^254976 mod p(x)` << 1, x^255040 mod p(x)` << 1 */
38 /* x^253952 mod p(x)` << 1, x^254016 mod p(x)` << 1 */
41 /* x^252928 mod p(x)` << 1, x^252992 mod p(x)` << 1 */
44 /* x^251904 mod p(x)` << 1, x^251968 mod p(x)` << 1 */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Dcrct10dif-vpmsum_asm.S21 /* x^261184 mod p(x), x^261120 mod p(x) */
24 /* x^260160 mod p(x), x^260096 mod p(x) */
27 /* x^259136 mod p(x), x^259072 mod p(x) */
30 /* x^258112 mod p(x), x^258048 mod p(x) */
33 /* x^257088 mod p(x), x^257024 mod p(x) */
36 /* x^256064 mod p(x), x^256000 mod p(x) */
39 /* x^255040 mod p(x), x^254976 mod p(x) */
42 /* x^254016 mod p(x), x^253952 mod p(x) */
45 /* x^252992 mod p(x), x^252928 mod p(x) */
48 /* x^251968 mod p(x), x^251904 mod p(x) */
[all …]
Dcrc32c-vpmsum_asm.S17 /* x^261120 mod p(x)` << 1, x^261184 mod p(x)` << 1 */
20 /* x^260096 mod p(x)` << 1, x^260160 mod p(x)` << 1 */
23 /* x^259072 mod p(x)` << 1, x^259136 mod p(x)` << 1 */
26 /* x^258048 mod p(x)` << 1, x^258112 mod p(x)` << 1 */
29 /* x^257024 mod p(x)` << 1, x^257088 mod p(x)` << 1 */
32 /* x^256000 mod p(x)` << 1, x^256064 mod p(x)` << 1 */
35 /* x^254976 mod p(x)` << 1, x^255040 mod p(x)` << 1 */
38 /* x^253952 mod p(x)` << 1, x^254016 mod p(x)` << 1 */
41 /* x^252928 mod p(x)` << 1, x^252992 mod p(x)` << 1 */
44 /* x^251904 mod p(x)` << 1, x^251968 mod p(x)` << 1 */
[all …]
/kernel/linux/linux-6.6/drivers/phy/microchip/
Dsparx5_serdes_regs.h35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
47 #define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\ argument
48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
[all …]
Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
[all …]
Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
[all …]
Dr300d.h70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
[all …]
Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
[all …]
Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
[all …]
Dr300d.h70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
[all …]
Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main_regs.h65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument
82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
[all …]
/kernel/linux/linux-6.6/lib/crypto/
Dchacha.c16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/kernel/linux/linux-5.10/lib/crypto/
Dchacha.c16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/verisilicon/
Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/hantro/
Drk3399_vpu_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/
Dregs.h36 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
40 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
44 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
48 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
52 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
56 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
61 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
62 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
65 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
69 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dregs.h45 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
49 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
53 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
57 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
61 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
65 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
70 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
71 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
74 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
78 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
[all …]

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