| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | xlnx,xps-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
18 maxItems: 1
20 clock-names:
24 maxItems: 1
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/ |
| D | xlnx,xps-timebase-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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| /kernel/linux/linux-5.10/arch/microblaze/boot/dts/ |
| D | system.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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| /kernel/linux/linux-6.6/arch/microblaze/boot/dts/ |
| D | system.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | of_xilinx_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
28 #define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */
29 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
31 /* Control/Status Register 0/1 bits */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
62 /* Clean previous status and enable the watchdog timer */ in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
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| /kernel/linux/linux-6.6/net/sunrpc/ |
| D | xprt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * - When a process places a call, it allocates a request slot if
13 * - Next, the caller puts together the RPC message, stuffs it into
15 * - xprt_transmit sends the message and installs the caller on the
17 * it installs a timer that is run after the packet's timeout has
19 * - When a packet arrives, the data_ready handler walks the list of
21 * caller is woken up, and the timer removed.
22 * - When no reply arrives within the timeout interval, the timer is
25 * of -ETIMEDOUT.
26 * - When the caller receives a notification from RPC that a reply arrived,
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | of_xilinx_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
28 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
29 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
31 /* Control/Status Register 0/1 bits */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
62 /* Clean previous status and enable the watchdog timer */ in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
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| /kernel/linux/linux-5.10/arch/sh/boot/dts/ |
| D | j2_mimas_v2.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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| /kernel/linux/linux-6.6/arch/sh/boot/dts/ |
| D | j2_mimas_v2.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_clock_utils.c | 1 // SPDX-License-Identifier: MIT
16 if (INTEL_GEN(gt->i915) >= 11) { in read_clock_frequency()
19 config = intel_uncore_read(gt->uncore, RPM_CONFIG0); in read_clock_frequency()
25 case 1: in read_clock_frequency()
30 } else if (INTEL_GEN(gt->i915) >= 9) { in read_clock_frequency()
31 if (IS_GEN9_LP(gt->i915)) in read_clock_frequency()
46 gt->clock_frequency = read_clock_frequency(gt); in intel_gt_init_clock_frequency()
49 gt->clock_frequency / 1000); in intel_gt_init_clock_frequency()
55 if (gt->clock_frequency != read_clock_frequency(gt)) { in intel_gt_check_clock_frequency()
56 dev_err(gt->i915->drm.dev, in intel_gt_check_clock_frequency()
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| /kernel/linux/linux-5.10/arch/microblaze/kernel/ |
| D | timer.c | 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
36 #define TCSR_MDT (1<<0)
37 #define TCSR_UDT (1<<1)
38 #define TCSR_GENT (1<<2)
39 #define TCSR_CAPT (1<<3)
40 #define TCSR_ARHT (1<<4)
41 #define TCSR_LOAD (1<<5)
42 #define TCSR_ENIT (1<<6)
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| /kernel/linux/linux-6.6/arch/microblaze/kernel/ |
| D | timer.c | 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
36 #define TCSR_MDT (1<<0)
37 #define TCSR_UDT (1<<1)
38 #define TCSR_GENT (1<<2)
39 #define TCSR_CAPT (1<<3)
40 #define TCSR_ARHT (1<<4)
41 #define TCSR_LOAD (1<<5)
42 #define TCSR_ENIT (1<<6)
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| /kernel/linux/linux-6.6/include/linux/sunrpc/ |
| D | xprt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define RPC_CWNDSCALE (1U << RPC_CWNDSHIFT)
30 #define RPC_MAXCWND(xprt) ((xprt)->max_reqs << RPC_CWNDSHIFT)
31 #define RPCXPRT_CONGESTED(xprt) ((xprt)->cong >= (xprt)->cwnd)
66 * This is the user-visible part
78 int rq_cong; /* has incremented xprt->cong */
107 ktime_t rq_rtt; /* round-trip time */
166 void (*timer)(struct rpc_xprt *xprt, struct rpc_task *task); member
195 #define XPRT_TRANSPORT_BC (1 << 31)
232 unsigned char resvport : 1, /* use a reserved port */
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| D | clnt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Declarations for the high-level RPC client interface
25 #include <linux/sunrpc/timer.h>
42 * The high-level client handle
58 struct rpc_stat * cl_stats; /* per-program statistics */
59 struct rpc_iostats * cl_metrics; /* per-client statistics */
61 unsigned int cl_softrtry : 1,/* soft timeouts */
62 cl_softerr : 1,/* Timeouts return errors */
63 cl_discrtry : 1,/* disconnect before retry */
64 cl_noretranstimeo: 1,/* No retransmit timeouts */
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| /kernel/linux/linux-5.10/drivers/input/serio/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
113 This driver provides support for the PS/2 ports on PA-RISC machines
130 The SDC itself contains a 10ms resolution timer/clock capable
131 of delivering interrupts on a periodic and one-shot basis.
132 The SDC may also be connected to a battery-backed real-time
133 clock, a basic audio waveform generator, and an HP-HIL Master
195 allocating minor 1 (that historically corresponds to /dev/psaux)
198 echo -n "serio_raw" > /sys/bus/serio/devices/serioX/drvctl
204 tristate "Xilinx XPS PS/2 Controller Support"
207 This driver supports XPS PS/2 IP from the Xilinx EDK on
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| /kernel/linux/linux-6.6/drivers/input/serio/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
113 This driver provides support for the PS/2 ports on PA-RISC machines
130 The SDC itself contains a 10ms resolution timer/clock capable
131 of delivering interrupts on a periodic and one-shot basis.
132 The SDC may also be connected to a battery-backed real-time
133 clock, a basic audio waveform generator, and an HP-HIL Master
196 allocating minor 1 (that historically corresponds to /dev/psaux)
199 echo -n "serio_raw" > /sys/bus/serio/devices/serioX/drvctl
205 tristate "Xilinx XPS PS/2 Controller Support"
208 This driver supports XPS PS/2 IP from the Xilinx EDK on
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| /kernel/linux/linux-6.6/drivers/pwm/ |
| D | pwm-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
41 return priv->max - cycles + 2; in xilinx_timer_tlr_cycles()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_clock_utils.c | 1 // SPDX-License-Identifier: MIT
19 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; in read_reference_ts_freq()
25 frac_freq = 1000000 / (frac_freq + 1); in read_reference_ts_freq()
82 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency()
97 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
104 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> in gen9_read_clock_frequency()
135 * 63:20 increments every 1/4 ns in g4x_read_clock_frequency()
138 * -> 63:32 increments every 1024 ns in g4x_read_clock_frequency()
154 return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000; in gen4_read_clock_frequency()
159 if (GRAPHICS_VER(uncore->i915) >= 11) in read_clock_frequency()
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| /kernel/linux/linux-5.10/include/linux/sunrpc/ |
| D | clnt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Declarations for the high-level RPC client interface
24 #include <linux/sunrpc/timer.h>
34 * The high-level client handle
49 struct rpc_stat * cl_stats; /* per-program statistics */
50 struct rpc_iostats * cl_metrics; /* per-client statistics */
52 unsigned int cl_softrtry : 1,/* soft timeouts */
53 cl_softerr : 1,/* Timeouts return errors */
54 cl_discrtry : 1,/* disconnect before retry */
55 cl_noretranstimeo: 1,/* No retransmit timeouts */
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| /kernel/linux/linux-5.10/drivers/char/xilinx_hwicap/ |
| D | xilinx_hwicap.c | 26 * (c) Copyright 2007-2008 Xilinx Inc.
36 * This is the code behind /dev/icap* -- it allows a user-space
64 * user-space application code that uses this device. The simplest
109 #define HWICAP_DEVICES 1
122 .FAR = 1,
140 .TIMER = UNIMPLEMENTED,
147 .FAR = 1,
165 .TIMER = UNIMPLEMENTED,
172 .FAR = 1,
190 .TIMER = 17,
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| /kernel/linux/linux-6.6/drivers/char/xilinx_hwicap/ |
| D | xilinx_hwicap.c | 26 * (c) Copyright 2007-2008 Xilinx Inc.
36 * This is the code behind /dev/icap* -- it allows a user-space
64 * user-space application code that uses this device. The simplest
109 #define HWICAP_DEVICES 1
124 .FAR = 1,
142 .TIMER = UNIMPLEMENTED,
149 .FAR = 1,
167 .TIMER = UNIMPLEMENTED,
174 .FAR = 1,
192 .TIMER = 17,
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| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | apm_32.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* -*- linux-c -*-
4 * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
16 * (Thanks to Ulrich Windl <Ulrich.Windl@rz.uni-regensburg.de>)
43 * 1.1: support user-space standby and suspend, power off after system
46 * is only incorrect by 30-60mS (vs. 1S previously) (Gabor J. Toth
48 * screen-blanking and gpm (Stephen Rothwell); Linux 1.99.4
63 * <echter@informatik.uni-rostock.de>
68 * Reset interrupt 0 timer to 100Hz after suspend
109 * <Walter.Hofmann@physik.stud.uni-erlangen.de>).
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| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | apm_32.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* -*- linux-c -*-
4 * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
16 * (Thanks to Ulrich Windl <Ulrich.Windl@rz.uni-regensburg.de>)
43 * 1.1: support user-space standby and suspend, power off after system
46 * is only incorrect by 30-60mS (vs. 1S previously) (Gabor J. Toth
48 * screen-blanking and gpm (Stephen Rothwell); Linux 1.99.4
63 * <echter@informatik.uni-rostock.de>
68 * Reset interrupt 0 timer to 100Hz after suspend
109 * <Walter.Hofmann@physik.stud.uni-erlangen.de>).
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| /kernel/linux/linux-5.10/drivers/block/ |
| D | xsysace.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 * The FSM itself is atomic-safe code which can be run from any
37 * 1. obtain the ace->lock spinlock.
38 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
56 * 1. ace_fsm_yield()
57 * - Call if need to poll for event.
58 * - clears the fsm_continue flag to exit the processing loop
59 * - reschedules the tasklet to run again as soon as possible
61 * - Call if an irq is expected from the HW
62 * - clears the fsm_continue flag to exit the processing loop
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| /kernel/linux/linux-5.10/net/sched/ |
| D | sch_fq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013-2015 Eric Dumazet <edumazet@google.com>
8 * Fast classification depends on skb->sk being set before reaching us.
17 * Transport (eg TCP) can set in sk->sk_pacing_rate a rate, enqueue a
22 * - lookup one RB tree (out of 1024 or more) to find the flow.
25 * - Use a special fifo for high prio packets
60 return (struct fq_skb_cb *)qdisc_skb_cb(skb)->data; in fq_skb_cb()
65 * If packets have monotically increasing time_to_send, they are placed in O(1)
74 unsigned long age; /* (jiffies | 1UL) when flow was emptied, for gc */
87 struct rb_node rate_node; /* anchor in q->delayed tree */
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