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Searched +full:zynqmp +full:- +full:dpdma (Results 1 – 16 of 16) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: "../dma-controller.yaml#"
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/kernel/linux/linux-6.6/drivers/dma/xilinx/
Dxilinx_dpdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
31 #include "../virt-dma.h"
33 /* DPDMA registers */
119 /* DPDMA descriptor fields */
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
181 * @hw: DPDMA hardware descriptor
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/kernel/linux/linux-5.10/drivers/dma/xilinx/
Dxilinx_dpdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
30 #include "../virt-dma.h"
32 /* DPDMA registers */
118 /* DPDMA descriptor fields */
141 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
179 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
180 * @hw: DPDMA hardware descriptor
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
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/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_disp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ZynqMP Display Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
24 /* The DPDMA is limited to 44 bit addressing. */
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/dma-mapping.h>
43 * --------
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/kernel/linux/linux-6.6/drivers/gpu/drm/xlnx/
Dzynqmp_disp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ZynqMP Display Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
24 /* The DPDMA is limited to 44 bit addressing. */
36 * enum zynqmp_dpsub_layer_id - Layer identifier
46 * enum zynqmp_dpsub_layer_mode - Layer mode
47 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
33 * --------
35 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
38 * +------------------------------------------------------------+
39 * +--------+ | +----------------+ +-----------+ |
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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/kernel/linux/linux-5.10/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
103 tristate "Analog Devices AXI-DMAC DMA support"
109 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
129 bool "ST-Ericsson COH901318 DMA support"
133 Enable support for ST-Ericsson COH 901 318 DMA.
152 tristate "SA-11x0 DMA support"
157 Support the DMA engine found on Intel StrongARM SA-1100 and
158 SA-1110 SoCs. This DMA engine can only be used with on-chip
217 This module can be found on Freescale Vybrid and LS-1 SoCs.
260 Enable support for the IMG multi-threaded DMA controller (MDC).
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/kernel/linux/linux-6.6/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
283 tristate "Intel integrated DMA 64-bit support"
319 accel-config) to continue function. It is expected that accel-config
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/kernel/linux/linux-6.6/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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