| /kernel/linux/linux-6.6/Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
[all …]
|
| /kernel/linux/linux-5.10/Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/ |
| D | xlnx,zynqmp-power.txt | 1 --------------------------------------------------------------------
3 --------------------------------------------------------------------
4 The zynqmp-power node describes the power management configurations.
8 - compatible: Must contain: "xlnx,zynqmp-power"
9 - interrupts: Interrupt specifier
12 - mbox-names : Name given to channels seen in the 'mboxes' property.
13 "tx" - Mailbox corresponding to transmit path
14 "rx" - Mailbox corresponding to receive path
15 - mboxes : Standard property to specify a Mailbox. Each value of
18 that will be the phandle to the intended sub-mailbox
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/reset/ |
| D | xlnx,zynqmp-power.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
37 - description: tx channel
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/ |
| D | xlnx,zynqmp-aes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
10 - Kalyani Akula <kalyani.akula@amd.com>
11 - Michal Simek <michal.simek@amd.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/ |
| D | xlnx,zynqmp-aes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
10 - Kalyani Akula <kalyani.akula@xilinx.com>
11 - Michal Simek <michal.simek@xilinx.com>
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
22 - compatible
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.txt | 1 -----------------------------------------------------------------
2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
3 -----------------------------------------------------------------
5 The zynqmp-firmware node describes the interface to platform firmware.
6 ZynqMP has an interface to communicate with secure firmware. Firmware
7 driver provides an interface to firmware APIs. Interface APIs can be
14 - compatible: Must contain any of below:
15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
16 "xlnx,versal-firmware" for Versal
17 - method: The method of calling the PM-API firmware layer.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,zynqmp-pcap-fpga.txt | 2 The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
3 Programmable Logic (PL). The configuration uses the firmware interface.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
14 #size-cells = <0x1>;
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | xlnx,zynqmp-clk.txt | 1 --------------------------------------------------------------------------
3 Zynq MPSoC firmware interface
4 --------------------------------------------------------------------------
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
[all …]
|
| D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
21 const: xlnx,versal-clk
23 "#clock-cells":
30 - description: reference clock
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,zynqmp-pcap-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
16 firmware interface.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/ |
| D | xlnx,zynqmp-nvmem.txt | 1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | xlnx,zynqmp-nvmem.txt | 1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
3 --------------------------------------------------------------------------
5 like soc revision, IDCODE... etc, By using the firmware interface.
8 - compatible: should be "xlnx,zynqmp-nvmem-fw"
14 -------
16 -------
17 firmware {
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | xlnx,zynqmp-reset.txt | 1 --------------------------------------------------------------------------
3 --------------------------------------------------------------------------
7 about zynqmp resets.
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
22 firmware {
23 zynqmp_firmware: zynqmp-firmware {
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
| D | xlnx,zynqmp-genpd.txt | 1 -----------------------------------------------------------
3 -----------------------------------------------------------
4 The binding for zynqmp-power-controller follow the common
7 [1] Documentation/devicetree/bindings/power/power-domain.yaml
12 - Below property should be in zynqmp-firmware node.
13 - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
16 include/dt-bindings/power/xlnx-zynqmp-power.h.
18 -------
20 -------
22 firmware {
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
[all …]
|
| /kernel/linux/linux-6.6/drivers/firmware/xilinx/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
|
| /kernel/linux/linux-5.10/drivers/firmware/xilinx/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
13 Firmware interface driver is used by different
14 drivers to communicate with the firmware for
16 Say yes to enable ZynqMP firmware interface driver.
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
23 Say yes to enable ZynqMP firmware interface debug APIs.
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | xlnx,zynqmp-gpio-modepin.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ZynqMP Mode Pin GPIO controller
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
15 - Piyush Mehta <piyush.mehta@amd.com>
19 const: xlnx,zynqmp-gpio-modepin
21 gpio-controller: true
23 "#gpio-cells":
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/xilinx/ |
| D | eemi.rst | 5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/xilinx/ |
| D | eemi.rst | 5 Xilinx Zynq MPSoC Firmware Interface
6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
8 ZynqMP has an interface to communicate with secure firmware. Firmware
9 driver provides an interface to firmware APIs. Interface APIs can be
13 ----------------------------------------------
23 ------
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
[all …]
|
| /kernel/linux/linux-5.10/drivers/nvmem/ |
| D | zynqmp_nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/nvmem-provider.h>
10 #include <linux/firmware/xlnx-zynqmp.h>
30 dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); in zynqmp_nvmem_read()
37 .name = "zynqmp-nvmem",
45 { .compatible = "xlnx,zynqmp-nvmem-fw", },
52 struct device *dev = &pdev->dev; in zynqmp_nvmem_probe()
57 return -ENOMEM; in zynqmp_nvmem_probe()
59 priv->dev = dev; in zynqmp_nvmem_probe()
64 priv->nvmem = devm_nvmem_register(dev, &econfig); in zynqmp_nvmem_probe()
[all …]
|
| /kernel/linux/linux-6.6/drivers/nvmem/ |
| D | zynqmp_nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/nvmem-provider.h>
10 #include <linux/firmware/xlnx-zynqmp.h>
30 dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); in zynqmp_nvmem_read()
37 .name = "zynqmp-nvmem",
45 { .compatible = "xlnx,zynqmp-nvmem-fw", },
52 struct device *dev = &pdev->dev; in zynqmp_nvmem_probe()
57 return -ENOMEM; in zynqmp_nvmem_probe()
59 priv->dev = dev; in zynqmp_nvmem_probe()
65 priv->nvmem = devm_nvmem_register(dev, &econfig); in zynqmp_nvmem_probe()
[all …]
|