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/kernel/linux/linux-5.10/Documentation/ABI/stable/
Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
39 and maintains its value through a system reset.
42 Register is reset only by a POR reset.
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/stable/
Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
39 and maintains its value through a system reset.
42 Register is reset only by a POR reset.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.txt1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
3 --------------------------------------------------------------------------
7 about zynqmp resets.
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
18 -------
20 -------
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dxlnx,zynqmp-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
10 - Piyush Mehta <piyush.mehta@amd.com>
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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Dzynqmp-zcu102-revB.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU102 RevB
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include "zynqmp-zcu102-revA.dts"
14 model = "ZynqMP ZCU102 RevB";
15 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
19 phy-handle = <&phyc>;
21 phyc: ethernet-phy@c {
22 #phy-cells = <0x1>;
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Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
14 #include "zynqmp.dtsi"
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
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Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
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Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/reset/
Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
37 - description: tx channel
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dsnps,dw-umctl2-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
17 16-bits or 32-bits or 64-bits wide.
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dmacb.txt4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
12 Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
13 Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
14 Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
[all …]
/kernel/linux/linux-6.6/drivers/reset/
Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
13 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
97 .reset = zynqmp_reset_reset,
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/reset-controller.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
14 #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
39 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_assert()
48 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_deassert()
59 err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val); in zynqmp_reset_status()
71 return zynqmp_pm_reset_assert(priv->data->reset_id + id, in zynqmp_reset_reset()
78 return reset_spec->args[0]; in zynqmp_reset_of_xlate()
92 .reset = zynqmp_reset_reset,
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
19 compatible = "xlnx,zynqmp";
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
20 model = "ZynqMP ZCU100 RevC";
[all …]
/kernel/linux/linux-5.10/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
21 #include <linux/io-64-nonatomic-lo-hi.h>
130 /* Reset values for data attributes */
143 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
151 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
167 * struct zynqmp_dma_desc_sw - Per Transaction structure
193 * struct zynqmp_dma_chan - Driver specific DMA channel structure
243 * struct zynqmp_dma_device - DMA device structure
261 lo_hi_writeq(value, chan->regs + reg); in zynqmp_dma_writeq()
[all …]
/kernel/linux/linux-6.6/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
128 /* Reset values for data attributes */
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
149 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
165 * struct zynqmp_dma_desc_sw - Per Transaction structure
191 * struct zynqmp_dma_chan - Driver specific DMA channel structure
241 * struct zynqmp_dma_device - DMA device structure
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_dpsub.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP DisplayPort Subsystem Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 #include <linux/dma-mapping.h>
35 /* -----------------------------------------------------------------------------
44 unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8); in zynqmp_dpsub_dumb_create()
47 args->pitch = ALIGN(pitch, dpsub->dma_align); in zynqmp_dpsub_dumb_create()
62 cmd.pitches[i] = ALIGN(cmd.pitches[i], dpsub->dma_align); in zynqmp_dpsub_fb_create()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
14 special extensions to add functionality, is a high-performance dual-port
21 const: ceva,ahci-1v84
29 dma-coherent: true
37 power-domains:
40 ceva,p0-cominit-params:
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