1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52
53 using namespace llvm;
54
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56 cl::desc("Enable the machine combiner pass"),
57 cl::init(true), cl::Hidden);
58
59 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
60 cl::desc("Enable the conditional branch "
61 "folding pass"),
62 cl::init(false), cl::Hidden);
63
LLVMInitializeX86Target()64 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
65 // Register the target.
66 RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
67 RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
68
69 PassRegistry &PR = *PassRegistry::getPassRegistry();
70 initializeGlobalISel(PR);
71 initializeWinEHStatePassPass(PR);
72 initializeFixupBWInstPassPass(PR);
73 initializeEvexToVexInstPassPass(PR);
74 initializeFixupLEAPassPass(PR);
75 initializeFPSPass(PR);
76 initializeX86CallFrameOptimizationPass(PR);
77 initializeX86CmovConverterPassPass(PR);
78 initializeX86ExpandPseudoPass(PR);
79 initializeX86ExecutionDomainFixPass(PR);
80 initializeX86DomainReassignmentPass(PR);
81 initializeX86AvoidSFBPassPass(PR);
82 initializeX86SpeculativeLoadHardeningPassPass(PR);
83 initializeX86FlagsCopyLoweringPassPass(PR);
84 initializeX86CondBrFoldingPassPass(PR);
85 initializeX86OptimizeLEAPassPass(PR);
86 }
87
createTLOF(const Triple & TT)88 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
89 if (TT.isOSBinFormatMachO()) {
90 if (TT.getArch() == Triple::x86_64)
91 return std::make_unique<X86_64MachoTargetObjectFile>();
92 return std::make_unique<TargetLoweringObjectFileMachO>();
93 }
94
95 if (TT.isOSFreeBSD())
96 return std::make_unique<X86FreeBSDTargetObjectFile>();
97 if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
98 return std::make_unique<X86LinuxNaClTargetObjectFile>();
99 if (TT.isOSSolaris())
100 return std::make_unique<X86SolarisTargetObjectFile>();
101 if (TT.isOSFuchsia())
102 return std::make_unique<X86FuchsiaTargetObjectFile>();
103 if (TT.isOSBinFormatELF())
104 return std::make_unique<X86ELFTargetObjectFile>();
105 if (TT.isOSBinFormatCOFF())
106 return std::make_unique<TargetLoweringObjectFileCOFF>();
107 llvm_unreachable("unknown subtarget type");
108 }
109
computeDataLayout(const Triple & TT)110 static std::string computeDataLayout(const Triple &TT) {
111 // X86 is little endian
112 std::string Ret = "e";
113
114 Ret += DataLayout::getManglingComponent(TT);
115 // X86 and x32 have 32 bit pointers.
116 if ((TT.isArch64Bit() &&
117 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
118 !TT.isArch64Bit())
119 Ret += "-p:32:32";
120
121 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
122 Ret += "-p270:32:32-p271:32:32-p272:64:64";
123
124 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
125 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
126 Ret += "-i64:64";
127 else if (TT.isOSIAMCU())
128 Ret += "-i64:32-f64:32";
129 else
130 Ret += "-f64:32:64";
131
132 // Some ABIs align long double to 128 bits, others to 32.
133 if (TT.isOSNaCl() || TT.isOSIAMCU())
134 ; // No f80
135 else if (TT.isArch64Bit() || TT.isOSDarwin())
136 Ret += "-f80:128";
137 else
138 Ret += "-f80:32";
139
140 if (TT.isOSIAMCU())
141 Ret += "-f128:32";
142
143 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
144 if (TT.isArch64Bit())
145 Ret += "-n8:16:32:64";
146 else
147 Ret += "-n8:16:32";
148
149 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
150 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
151 Ret += "-a:0:32-S32";
152 else
153 Ret += "-S128";
154
155 return Ret;
156 }
157
getEffectiveRelocModel(const Triple & TT,bool JIT,Optional<Reloc::Model> RM)158 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
159 bool JIT,
160 Optional<Reloc::Model> RM) {
161 bool is64Bit = TT.getArch() == Triple::x86_64;
162 if (!RM.hasValue()) {
163 // JIT codegen should use static relocations by default, since it's
164 // typically executed in process and not relocatable.
165 if (JIT)
166 return Reloc::Static;
167
168 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
169 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
170 // use static relocation model by default.
171 if (TT.isOSDarwin()) {
172 if (is64Bit)
173 return Reloc::PIC_;
174 return Reloc::DynamicNoPIC;
175 }
176 if (TT.isOSWindows() && is64Bit)
177 return Reloc::PIC_;
178 return Reloc::Static;
179 }
180
181 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
182 // is defined as a model for code which may be used in static or dynamic
183 // executables but not necessarily a shared library. On X86-32 we just
184 // compile in -static mode, in x86-64 we use PIC.
185 if (*RM == Reloc::DynamicNoPIC) {
186 if (is64Bit)
187 return Reloc::PIC_;
188 if (!TT.isOSDarwin())
189 return Reloc::Static;
190 }
191
192 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
193 // the Mach-O file format doesn't support it.
194 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
195 return Reloc::PIC_;
196
197 return *RM;
198 }
199
getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,bool JIT,bool Is64Bit)200 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
201 bool JIT, bool Is64Bit) {
202 if (CM) {
203 if (*CM == CodeModel::Tiny)
204 report_fatal_error("Target does not support the tiny CodeModel", false);
205 return *CM;
206 }
207 if (JIT)
208 return Is64Bit ? CodeModel::Large : CodeModel::Small;
209 return CodeModel::Small;
210 }
211
212 /// Create an X86 target.
213 ///
X86TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)214 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
215 StringRef CPU, StringRef FS,
216 const TargetOptions &Options,
217 Optional<Reloc::Model> RM,
218 Optional<CodeModel::Model> CM,
219 CodeGenOpt::Level OL, bool JIT)
220 : LLVMTargetMachine(
221 T, computeDataLayout(TT), TT, CPU, FS, Options,
222 getEffectiveRelocModel(TT, JIT, RM),
223 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
224 OL),
225 TLOF(createTLOF(getTargetTriple())) {
226 // On PS4, the "return address" of a 'noreturn' call must still be within
227 // the calling function, and TrapUnreachable is an easy way to get that.
228 if (TT.isPS4() || TT.isOSBinFormatMachO()) {
229 this->Options.TrapUnreachable = true;
230 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
231 }
232
233 setMachineOutliner(true);
234
235 initAsmInfo();
236 }
237
238 X86TargetMachine::~X86TargetMachine() = default;
239
240 const X86Subtarget *
getSubtargetImpl(const Function & F) const241 X86TargetMachine::getSubtargetImpl(const Function &F) const {
242 Attribute CPUAttr = F.getFnAttribute("target-cpu");
243 Attribute FSAttr = F.getFnAttribute("target-features");
244
245 StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
246 ? CPUAttr.getValueAsString()
247 : (StringRef)TargetCPU;
248 StringRef FS = !FSAttr.hasAttribute(Attribute::None)
249 ? FSAttr.getValueAsString()
250 : (StringRef)TargetFS;
251
252 SmallString<512> Key;
253 Key.reserve(CPU.size() + FS.size());
254 Key += CPU;
255 Key += FS;
256
257 // FIXME: This is related to the code below to reset the target options,
258 // we need to know whether or not the soft float flag is set on the
259 // function before we can generate a subtarget. We also need to use
260 // it as a key for the subtarget since that can be the only difference
261 // between two functions.
262 bool SoftFloat =
263 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
264 // If the soft float attribute is set on the function turn on the soft float
265 // subtarget feature.
266 if (SoftFloat)
267 Key += FS.empty() ? "+soft-float" : ",+soft-float";
268
269 // Keep track of the key width after all features are added so we can extract
270 // the feature string out later.
271 unsigned CPUFSWidth = Key.size();
272
273 // Extract prefer-vector-width attribute.
274 unsigned PreferVectorWidthOverride = 0;
275 if (F.hasFnAttribute("prefer-vector-width")) {
276 StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
277 unsigned Width;
278 if (!Val.getAsInteger(0, Width)) {
279 Key += ",prefer-vector-width=";
280 Key += Val;
281 PreferVectorWidthOverride = Width;
282 }
283 }
284
285 // Extract min-legal-vector-width attribute.
286 unsigned RequiredVectorWidth = UINT32_MAX;
287 if (F.hasFnAttribute("min-legal-vector-width")) {
288 StringRef Val =
289 F.getFnAttribute("min-legal-vector-width").getValueAsString();
290 unsigned Width;
291 if (!Val.getAsInteger(0, Width)) {
292 Key += ",min-legal-vector-width=";
293 Key += Val;
294 RequiredVectorWidth = Width;
295 }
296 }
297
298 // Extracted here so that we make sure there is backing for the StringRef. If
299 // we assigned earlier, its possible the SmallString reallocated leaving a
300 // dangling StringRef.
301 FS = Key.slice(CPU.size(), CPUFSWidth);
302
303 auto &I = SubtargetMap[Key];
304 if (!I) {
305 // This needs to be done before we create a new subtarget since any
306 // creation will depend on the TM and the code generation flags on the
307 // function that reside in TargetOptions.
308 resetTargetOptions(F);
309 I = std::make_unique<X86Subtarget>(
310 TargetTriple, CPU, FS, *this,
311 MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
312 RequiredVectorWidth);
313 }
314 return I.get();
315 }
316
317 //===----------------------------------------------------------------------===//
318 // Command line options for x86
319 //===----------------------------------------------------------------------===//
320 static cl::opt<bool>
321 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
322 cl::desc("Minimize AVX to SSE transition penalty"),
323 cl::init(true));
324
325 //===----------------------------------------------------------------------===//
326 // X86 TTI query.
327 //===----------------------------------------------------------------------===//
328
329 TargetTransformInfo
getTargetTransformInfo(const Function & F)330 X86TargetMachine::getTargetTransformInfo(const Function &F) {
331 return TargetTransformInfo(X86TTIImpl(this, F));
332 }
333
334 //===----------------------------------------------------------------------===//
335 // Pass Pipeline Configuration
336 //===----------------------------------------------------------------------===//
337
338 namespace {
339
340 /// X86 Code Generator Pass Configuration Options.
341 class X86PassConfig : public TargetPassConfig {
342 public:
X86PassConfig(X86TargetMachine & TM,PassManagerBase & PM)343 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
344 : TargetPassConfig(TM, PM) {}
345
getX86TargetMachine() const346 X86TargetMachine &getX86TargetMachine() const {
347 return getTM<X86TargetMachine>();
348 }
349
350 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const351 createMachineScheduler(MachineSchedContext *C) const override {
352 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
353 DAG->addMutation(createX86MacroFusionDAGMutation());
354 return DAG;
355 }
356
357 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const358 createPostMachineScheduler(MachineSchedContext *C) const override {
359 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
360 DAG->addMutation(createX86MacroFusionDAGMutation());
361 return DAG;
362 }
363
364 void addIRPasses() override;
365 bool addInstSelector() override;
366 bool addIRTranslator() override;
367 bool addLegalizeMachineIR() override;
368 bool addRegBankSelect() override;
369 bool addGlobalInstructionSelect() override;
370 bool addILPOpts() override;
371 bool addPreISel() override;
372 void addMachineSSAOptimization() override;
373 void addPreRegAlloc() override;
374 void addPostRegAlloc() override;
375 void addPreEmitPass() override;
376 void addPreEmitPass2() override;
377 void addPreSched2() override;
378
379 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
380 };
381
382 class X86ExecutionDomainFix : public ExecutionDomainFix {
383 public:
384 static char ID;
X86ExecutionDomainFix()385 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
getPassName() const386 StringRef getPassName() const override {
387 return "X86 Execution Dependency Fix";
388 }
389 };
390 char X86ExecutionDomainFix::ID;
391
392 } // end anonymous namespace
393
394 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
395 "X86 Execution Domain Fix", false, false)
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)396 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
397 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
398 "X86 Execution Domain Fix", false, false)
399
400 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
401 return new X86PassConfig(*this, PM);
402 }
403
addIRPasses()404 void X86PassConfig::addIRPasses() {
405 addPass(createAtomicExpandPass());
406
407 TargetPassConfig::addIRPasses();
408
409 if (TM->getOptLevel() != CodeGenOpt::None)
410 addPass(createInterleavedAccessPass());
411
412 // Add passes that handle indirect branch removal and insertion of a retpoline
413 // thunk. These will be a no-op unless a function subtarget has the retpoline
414 // feature enabled.
415 addPass(createIndirectBrExpandPass());
416
417 // Add Control Flow Guard checks.
418 const Triple &TT = TM->getTargetTriple();
419 if (TT.isOSWindows()) {
420 if (TT.getArch() == Triple::x86_64) {
421 addPass(createCFGuardDispatchPass());
422 } else {
423 addPass(createCFGuardCheckPass());
424 }
425 }
426 }
427
addInstSelector()428 bool X86PassConfig::addInstSelector() {
429 // Install an instruction selector.
430 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
431
432 // For ELF, cleanup any local-dynamic TLS accesses.
433 if (TM->getTargetTriple().isOSBinFormatELF() &&
434 getOptLevel() != CodeGenOpt::None)
435 addPass(createCleanupLocalDynamicTLSPass());
436
437 addPass(createX86GlobalBaseRegPass());
438 return false;
439 }
440
addIRTranslator()441 bool X86PassConfig::addIRTranslator() {
442 addPass(new IRTranslator());
443 return false;
444 }
445
addLegalizeMachineIR()446 bool X86PassConfig::addLegalizeMachineIR() {
447 addPass(new Legalizer());
448 return false;
449 }
450
addRegBankSelect()451 bool X86PassConfig::addRegBankSelect() {
452 addPass(new RegBankSelect());
453 return false;
454 }
455
addGlobalInstructionSelect()456 bool X86PassConfig::addGlobalInstructionSelect() {
457 addPass(new InstructionSelect());
458 return false;
459 }
460
addILPOpts()461 bool X86PassConfig::addILPOpts() {
462 if (EnableCondBrFoldingPass)
463 addPass(createX86CondBrFolding());
464 addPass(&EarlyIfConverterID);
465 if (EnableMachineCombinerPass)
466 addPass(&MachineCombinerID);
467 addPass(createX86CmovConverterPass());
468 return true;
469 }
470
addPreISel()471 bool X86PassConfig::addPreISel() {
472 // Only add this pass for 32-bit x86 Windows.
473 const Triple &TT = TM->getTargetTriple();
474 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
475 addPass(createX86WinEHStatePass());
476 return true;
477 }
478
addPreRegAlloc()479 void X86PassConfig::addPreRegAlloc() {
480 if (getOptLevel() != CodeGenOpt::None) {
481 addPass(&LiveRangeShrinkID);
482 addPass(createX86FixupSetCC());
483 addPass(createX86OptimizeLEAs());
484 addPass(createX86CallFrameOptimization());
485 addPass(createX86AvoidStoreForwardingBlocks());
486 }
487
488 addPass(createX86SpeculativeLoadHardeningPass());
489 addPass(createX86FlagsCopyLoweringPass());
490 addPass(createX86WinAllocaExpander());
491 }
addMachineSSAOptimization()492 void X86PassConfig::addMachineSSAOptimization() {
493 addPass(createX86DomainReassignmentPass());
494 TargetPassConfig::addMachineSSAOptimization();
495 }
496
addPostRegAlloc()497 void X86PassConfig::addPostRegAlloc() {
498 addPass(createX86FloatingPointStackifierPass());
499 }
500
addPreSched2()501 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
502
addPreEmitPass()503 void X86PassConfig::addPreEmitPass() {
504 if (getOptLevel() != CodeGenOpt::None) {
505 addPass(new X86ExecutionDomainFix());
506 addPass(createBreakFalseDeps());
507 }
508
509 addPass(createX86IndirectBranchTrackingPass());
510
511 if (UseVZeroUpper)
512 addPass(createX86IssueVZeroUpperPass());
513
514 if (getOptLevel() != CodeGenOpt::None) {
515 addPass(createX86FixupBWInsts());
516 addPass(createX86PadShortFunctions());
517 addPass(createX86FixupLEAs());
518 addPass(createX86EvexToVexInsts());
519 }
520 addPass(createX86DiscriminateMemOpsPass());
521 addPass(createX86InsertPrefetchPass());
522 }
523
addPreEmitPass2()524 void X86PassConfig::addPreEmitPass2() {
525 const Triple &TT = TM->getTargetTriple();
526 const MCAsmInfo *MAI = TM->getMCAsmInfo();
527
528 addPass(createX86RetpolineThunksPass());
529
530 // Insert extra int3 instructions after trailing call instructions to avoid
531 // issues in the unwinder.
532 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
533 addPass(createX86AvoidTrailingCallPass());
534
535 // Verify basic block incoming and outgoing cfa offset and register values and
536 // correct CFA calculation rule where needed by inserting appropriate CFI
537 // instructions.
538 if (!TT.isOSDarwin() &&
539 (!TT.isOSWindows() ||
540 MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
541 addPass(createCFIInstrInserter());
542 // Identify valid longjmp targets for Windows Control Flow Guard.
543 if (TT.isOSWindows())
544 addPass(createCFGuardLongjmpPass());
545 }
546
getCSEConfig() const547 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
548 return getStandardCSEConfigForOpt(TM->getOptLevel());
549 }
550