1 /* ---------------------------------------------------------------------------- 2 * Copyright (c) Huawei Technologies Co., Ltd. 2022-2023. All rights reserved. 3 * Description : CPU Register Defines Headfile 4 * Author: Huawei LiteOS Team 5 * Create : 2022-12-20 6 * Redistribution and use in source and binary forms, with or without modification, 7 * are permitted provided that the following conditions are met: 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 11 * of conditions and the following disclaimer in the documentation and/or other materials 12 * provided with the distribution. 13 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 14 * to endorse or promote products derived from this software without specific prior written 15 * permission. 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * ---------------------------------------------------------------------------- */ 28 29 #ifndef _ARCH_REGS_H 30 #define _ARCH_REGS_H 31 32 #include "los_typedef.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif /* __cplusplus */ 37 38 #define UINT64_SHIFT_32_BIT 32 39 40 #define ASM_STR(x) #x 41 42 #define READ_CSR(csrReg) ({ UINT32 tmp_; \ 43 asm volatile ("csrr %0, " ASM_STR(csrReg) : "=r"(tmp_)); \ 44 tmp_;}) \ 45 46 #define WRITE_CSR(csrReg, csrVal) do { \ 47 if (__builtin_constant_p(csrVal) && (UINT32)(csrVal) < 32) { \ 48 asm volatile ("csrw " ASM_STR(csrReg) ", %0" :: "i"(csrVal)); \ 49 } else { \ 50 asm volatile ("csrw " ASM_STR(csrReg) ", %0" :: "r"(csrVal)); \ 51 } \ 52 } while (0) 53 54 #define SET_CSR(csrReg, csrBit) ({ UINT32 tmp_; \ 55 if (__builtin_constant_p(csrBit) && (UINT32)(csrBit) < 32) { \ 56 asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ 57 } else { \ 58 asm volatile ("csrrs %0, " #csrReg ", %1" : "=r"(tmp_) : "r"(csrBit)); \ 59 } \ 60 tmp_;}) 61 62 #define CLEAR_CSR(csrReg, csrBit) ({ UINT32 tmp_; \ 63 if (__builtin_constant_p(csrBit) && (UINT32)(csrBit) < 32) { \ 64 asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "i"(csrBit)); \ 65 } else { \ 66 asm volatile ("csrrc %0, " #csrReg ", %1" : "=r"(tmp_) : "r"(csrBit)); \ 67 } \ 68 tmp_; }) 69 70 #define READ_CUSTOM_CSR(csrReg) ({ UINT32 tmp_; \ 71 asm volatile ("csrr %0, %1" : "=r"(tmp_) : "i"(csrReg)); \ 72 tmp_; }) 73 74 #define WRITE_CUSTOM_CSR_VAL(csrRegAddr, csrVal) do { \ 75 if (__builtin_constant_p(csrVal)) { \ 76 asm volatile("li t0," "%0" : : "i"(csrVal)); \ 77 } else { \ 78 asm volatile("mv t0," "%0" : : "r"(csrVal)); \ 79 } \ 80 asm volatile("csrw %0, t0" :: "i"(csrRegAddr)); \ 81 } while (0) 82 83 #define SET_CUSTOM_CSR(csrRegAddr, csrBit) do { \ 84 if (__builtin_constant_p(csrBit) && (UINT32)(csrBit) < 32) { \ 85 asm volatile("li t0," "%0" : : "i"(csrBit)); \ 86 } else { \ 87 asm volatile("mv t0," "%0" : : "r"(csrBit)); \ 88 } \ 89 asm volatile("csrs %0, t0" :: "i"(csrRegAddr)); \ 90 } while (0) 91 92 #define CLEAR_CUSTOM_CSR(csrRegAddr, csrBit) do { \ 93 if (__builtin_constant_p(csrBit) && (UINT32)(csrBit) < 32) { \ 94 asm volatile("li t0," "%0" : : "i"(csrBit)); \ 95 } else { \ 96 asm volatile("mv t0," "%0" : : "r"(csrBit)); \ 97 } \ 98 asm volatile("csrc %0, t0" :: "i"(csrRegAddr)); \ 99 } while (0) 100 101 #define READ_CSR32_BIT64(addrl, addrh, val) do { \ 102 UINT32 valueLo, valueHi, valueHiTmp; \ 103 valueHiTmp = READ_CSR(addrh); \ 104 valueLo = READ_CSR(addrl); \ 105 valueHi = READ_CSR(addrh); \ 106 if (valueHi != valueHiTmp) { \ 107 valueLo = READ_CSR(addrl); \ 108 } \ 109 val = valueLo + (((UINT64)valueHi) << UINT64_SHIFT_32_BIT); \ 110 } while (0) 111 112 #define WRITE_CSR32_BIT64(addrl, addrh, val) do { \ 113 WRITE_CSR(addrl, (val) & UINT32_MAX); \ 114 WRITE_CSR(addrh, ((UINT64)(val) >> 32) & UINT32_MAX); \ 115 } while (0) 116 117 #ifdef __cplusplus 118 } 119 #endif /* __cplusplus */ 120 121 #endif /* _ARCH_CACHE_H */ 122