1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: BARRIER 15 * 16 * Create: 2021-07-01 17 */ 18 19 #ifndef ARCH_BARRIER_H 20 #define ARCH_BARRIER_H 21 22 #ifdef __cplusplus 23 #if __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 #endif /* __cplusplus */ 27 28 #ifdef dsb 29 #undef dsb 30 #endif 31 #define dsb() __asm__ __volatile__("fence":::"memory") 32 33 #ifdef isb 34 #undef isb 35 #endif 36 #define isb() __asm__ __volatile__("fence":::"memory") 37 38 #ifdef nop 39 #undef nop 40 #endif 41 #define nop() __asm__ __volatile__("nop"); 42 43 #ifdef wfi 44 #undef wfi 45 #endif 46 #define wfi() __asm__ __volatile__("wfi") 47 48 #define get_int_status() !(read_csr(mstatus) & MSTATUS_MIE) 49 #define int_enter_lock() clear_csr(mstatus, MSTATUS_MIE) 50 #define int_exit_lock() set_csr(mstatus, MSTATUS_MIE) 51 52 #define int_disable_fault_exception() 53 #define int_enable_fault_exception() 54 55 #define get_temp_lr(temp_lr) __asm volatile("mv %0, x1" : "=r"(temp_lr)) 56 #define get_temp_pc(temp_pc) __asm volatile("csrr %0, mepc" : "=r"(temp_pc)) 57 #define get_temp_sp(temp_sp) __asm volatile("mv %0, sp" : "=r"(temp_sp)) 58 59 #ifdef __cplusplus 60 #if __cplusplus 61 } 62 #endif /* __cplusplus */ 63 #endif /* __cplusplus */ 64 65 #endif // BARRIER_H