1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * MSGBUF network driver ioctl/indication encoding 4 * Broadcom 802.11abg Networking Device Driver 5 * 6 * Definitions subject to change without notice. 7 * 8 * Copyright (C) 1999-2019, Broadcom. 9 * 10 * Unless you and Broadcom execute a separate written software license 11 * agreement governing use of this software, this software is licensed to you 12 * under the terms of the GNU General Public License version 2 (the "GPL"), 13 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 14 * following added to such license: 15 * 16 * As a special exception, the copyright holders of this software give you 17 * permission to link this software with independent modules, and to copy and 18 * distribute the resulting executable under terms of your choice, provided that 19 * you also meet, for each linked independent module, the terms and conditions of 20 * the license of that module. An independent module is a module which is not 21 * derived from this software. The special exception does not apply to any 22 * modifications of the software. 23 * 24 * Notwithstanding the above, under no circumstances may you combine this 25 * software in any way with any other Broadcom software provided under a license 26 * other than the GPL, without Broadcom's express prior written consent. 27 * 28 * 29 * <<Broadcom-WL-IPTag/Open:>> 30 * 31 * $Id: bcmmsgbuf.h 814986 2019-04-15 21:18:21Z $ 32 */ 33 #ifndef _bcmmsgbuf_h_ 34 #define _bcmmsgbuf_h_ 35 36 #include <ethernet.h> 37 #include <wlioctl.h> 38 #include <bcmpcie.h> 39 40 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN 41 42 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */ 43 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1) 44 45 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */ 46 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1) 47 48 #define H2DRING_TXPOST_ITEMSIZE 48 49 #define H2DRING_RXPOST_ITEMSIZE 32 50 #define H2DRING_CTRL_SUB_ITEMSIZE 40 51 52 #define D2HRING_TXCMPLT_ITEMSIZE 24 53 #define D2HRING_RXCMPLT_ITEMSIZE 40 54 55 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16 56 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32 57 58 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24 59 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE 60 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE 61 62 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20 63 64 #define H2DRING_TXPOST_MAX_ITEM 512 65 #define H2DRING_RXPOST_MAX_ITEM 512 66 #define H2DRING_CTRL_SUB_MAX_ITEM 64 67 #define D2HRING_TXCMPLT_MAX_ITEM 1024 68 #define D2HRING_RXCMPLT_MAX_ITEM 512 69 70 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32 71 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32 72 73 #define D2HRING_EDL_HDR_SIZE 48u 74 #define D2HRING_EDL_ITEMSIZE 2048u 75 #define D2HRING_EDL_MAX_ITEM 256u 76 #define D2HRING_EDL_WATERMARK (D2HRING_EDL_MAX_ITEM >> 5u) 77 78 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64 79 80 enum { 81 DNGL_TO_HOST_MSGBUF, 82 HOST_TO_DNGL_MSGBUF 83 }; 84 85 enum { 86 HOST_TO_DNGL_TXP_DATA, 87 HOST_TO_DNGL_RXP_DATA, 88 HOST_TO_DNGL_CTRL, 89 DNGL_TO_HOST_DATA, 90 DNGL_TO_HOST_CTRL 91 }; 92 93 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE 94 #define PCIEDEV_FIRMWARE_TSINFO 0x1 95 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1 96 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2 97 #define PCIEDEV_BTLOG_POST 0x3 98 #define PCIEDEV_BT_SNAPSHOT_POST 0x4 99 100 #ifdef PCIE_API_REV1 101 102 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0) 103 104 #define BCMMSGBUF_API_IFIDX(a) 0 105 #define BCMMSGBUF_API_SEQNUM(a) 0 106 #define BCMMSGBUF_IOCTL_XTID(a) 0 107 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id) 108 109 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b) 110 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b) 111 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b)) 112 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b) 113 114 #else /* PCIE_API_REV1 */ 115 116 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id) 117 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id) 118 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no) 119 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id) 120 121 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b)) 122 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b)) 123 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b)) 124 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b)) 125 126 #endif /* PCIE_API_REV1 */ 127 128 /* utility data structures */ 129 130 union addr64 { 131 struct { 132 uint32 low; 133 uint32 high; 134 }; 135 struct { 136 uint32 low_addr; 137 uint32 high_addr; 138 }; 139 uint64 u64; 140 } DECLSPEC_ALIGN(8); 141 142 typedef union addr64 bcm_addr64_t; 143 144 /* IOCTL req Hdr */ 145 /* cmn Msg Hdr */ 146 typedef struct cmn_msg_hdr { 147 /** message type */ 148 uint8 msg_type; 149 /** interface index this is valid for */ 150 uint8 if_id; 151 /* flags */ 152 uint8 flags; 153 /** sequence number */ 154 uint8 epoch; 155 /** packet Identifier for the associated host buffer */ 156 uint32 request_id; 157 } cmn_msg_hdr_t; 158 159 /** message type */ 160 typedef enum bcmpcie_msgtype { 161 MSG_TYPE_GEN_STATUS = 0x1, 162 MSG_TYPE_RING_STATUS = 0x2, 163 MSG_TYPE_FLOW_RING_CREATE = 0x3, 164 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4, 165 /* Enum value as copied from BISON 7.15: new generic message */ 166 MSG_TYPE_RING_CREATE_CMPLT = 0x4, 167 MSG_TYPE_FLOW_RING_DELETE = 0x5, 168 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6, 169 /* Enum value as copied from BISON 7.15: new generic message */ 170 MSG_TYPE_RING_DELETE_CMPLT = 0x6, 171 MSG_TYPE_FLOW_RING_FLUSH = 0x7, 172 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8, 173 MSG_TYPE_IOCTLPTR_REQ = 0x9, 174 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA, 175 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB, 176 MSG_TYPE_IOCTL_CMPLT = 0xC, 177 MSG_TYPE_EVENT_BUF_POST = 0xD, 178 MSG_TYPE_WL_EVENT = 0xE, 179 MSG_TYPE_TX_POST = 0xF, 180 MSG_TYPE_TX_STATUS = 0x10, 181 MSG_TYPE_RXBUF_POST = 0x11, 182 MSG_TYPE_RX_CMPLT = 0x12, 183 MSG_TYPE_LPBK_DMAXFER = 0x13, 184 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14, 185 MSG_TYPE_FLOW_RING_RESUME = 0x15, 186 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16, 187 MSG_TYPE_FLOW_RING_SUSPEND = 0x17, 188 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18, 189 MSG_TYPE_INFO_BUF_POST = 0x19, 190 MSG_TYPE_INFO_BUF_CMPLT = 0x1A, 191 MSG_TYPE_H2D_RING_CREATE = 0x1B, 192 MSG_TYPE_D2H_RING_CREATE = 0x1C, 193 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D, 194 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E, 195 MSG_TYPE_H2D_RING_CONFIG = 0x1F, 196 MSG_TYPE_D2H_RING_CONFIG = 0x20, 197 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21, 198 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22, 199 MSG_TYPE_H2D_MAILBOX_DATA = 0x23, 200 MSG_TYPE_D2H_MAILBOX_DATA = 0x24, 201 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25, 202 MSG_TYPE_HOSTTIMSTAMP = 0x26, 203 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27, 204 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28, 205 MSG_TYPE_SNAPSHOT_UPLOAD = 0x29, 206 MSG_TYPE_SNAPSHOT_CMPLT = 0x2A, 207 MSG_TYPE_H2D_RING_DELETE = 0x2B, 208 MSG_TYPE_D2H_RING_DELETE = 0x2C, 209 MSG_TYPE_H2D_RING_DELETE_CMPLT = 0x2D, 210 MSG_TYPE_D2H_RING_DELETE_CMPLT = 0x2E, 211 MSG_TYPE_API_MAX_RSVD = 0x3F 212 } bcmpcie_msg_type_t; 213 214 typedef enum bcmpcie_msgtype_int { 215 MSG_TYPE_INTERNAL_USE_START = 0x40, 216 MSG_TYPE_EVENT_PYLD = 0x41, 217 MSG_TYPE_IOCT_PYLD = 0x42, 218 MSG_TYPE_RX_PYLD = 0x43, 219 MSG_TYPE_HOST_FETCH = 0x44, 220 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45, 221 MSG_TYPE_TXMETADATA_PYLD = 0x46, 222 MSG_TYPE_INDX_UPDATE = 0x47, 223 MSG_TYPE_INFO_PYLD = 0x48, 224 MSG_TYPE_TS_EVENT_PYLD = 0x49, 225 MSG_TYPE_PVT_BTLOG_CMPLT = 0x4A, 226 MSG_TYPE_BTLOG_PYLD = 0x4B, 227 MSG_TYPE_HMAPTEST_PYLD = 0x4C, 228 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT = 0x4D, 229 MSG_TYPE_BT_SNAPSHOT_PYLD = 0x4E 230 } bcmpcie_msgtype_int_t; 231 232 typedef enum bcmpcie_msgtype_u { 233 MSG_TYPE_TX_BATCH_POST = 0x80, 234 MSG_TYPE_IOCTL_REQ = 0x81, 235 MSG_TYPE_HOST_EVNT = 0x82, /* console related */ 236 MSG_TYPE_LOOPBACK = 0x83 237 } bcmpcie_msgtype_u_t; 238 239 /** 240 * D2H ring host wakeup soft doorbell, override the PCIE doorbell. 241 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE 242 * Transl0 to write specified value to host address. 243 * 244 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register 245 * and value is Core/Thread context. Host will ensure routing the 32bit address 246 * offerred to PCIE to the mapped register. 247 * 248 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL 249 */ 250 typedef struct bcmpcie_soft_doorbell { 251 uint32 value; /* host defined value to be written, eg HW threadid */ 252 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */ 253 uint16 items; /* interrupt coalescing: item count before wakeup */ 254 uint16 msecs; /* interrupt coalescing: timeout in millisecs */ 255 } bcmpcie_soft_doorbell_t; 256 257 /** 258 * D2H interrupt using MSI instead of INTX 259 * Host configures MSI vector offset for each D2H interrupt 260 * 261 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL 262 */ 263 typedef enum bcmpcie_msi_intr_idx { 264 MSI_INTR_IDX_CTRL_CMPL_RING = 0, 265 MSI_INTR_IDX_TXP_CMPL_RING = 1, 266 MSI_INTR_IDX_RXP_CMPL_RING = 2, 267 MSI_INTR_IDX_INFO_CMPL_RING = 3, 268 MSI_INTR_IDX_MAILBOX = 4, 269 MSI_INTR_IDX_MAX = 5 270 } bcmpcie_msi_intr_idx_t; 271 272 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0 273 typedef enum bcmpcie_msi_offset_type { 274 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2, 275 BCMPCIE_D2H_MSI_OFFSET_MB1 = 3, 276 BCMPCIE_D2H_MSI_OFFSET_DB0 = 4, 277 BCMPCIE_D2H_MSI_OFFSET_DB1 = 5, 278 BCMPCIE_D2H_MSI_OFFSET_H1_DB0 = 6, 279 BCMPCIE_D2H_MSI_OFFSET_MAX = 7 280 } bcmpcie_msi_offset_type_t; 281 282 typedef struct bcmpcie_msi_offset { 283 uint16 intr_idx; /* interrupt index */ 284 uint16 msi_offset; /* msi vector offset */ 285 } bcmpcie_msi_offset_t; 286 287 typedef struct bcmpcie_msi_offset_config { 288 uint32 len; 289 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX]; 290 } bcmpcie_msi_offset_config_t; 291 292 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1 293 294 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE 295 296 /* if_id */ 297 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5 298 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7 299 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \ 300 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 301 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0 302 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F 303 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \ 304 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 305 306 /* flags */ 307 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1 308 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2 309 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4 310 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80 311 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80 312 313 /* IOCTL request message */ 314 typedef struct ioctl_req_msg { 315 /** common message header */ 316 cmn_msg_hdr_t cmn_hdr; 317 /** ioctl command type */ 318 uint32 cmd; 319 /** ioctl transaction ID, to pair with a ioctl response */ 320 uint16 trans_id; 321 /** input arguments buffer len */ 322 uint16 input_buf_len; 323 /** expected output len */ 324 uint16 output_buf_len; 325 /** to align the host address on 8 byte boundary */ 326 uint16 rsvd[3]; 327 /** always align on 8 byte boundary */ 328 bcm_addr64_t host_input_buf_addr; 329 /* rsvd */ 330 uint32 rsvd1[2]; 331 } ioctl_req_msg_t; 332 333 /** buffer post messages for device to use to return IOCTL responses, Events */ 334 typedef struct ioctl_resp_evt_buf_post_msg { 335 /** common message header */ 336 cmn_msg_hdr_t cmn_hdr; 337 /** length of the host buffer supplied */ 338 uint16 host_buf_len; 339 /** to align the host address on 8 byte boundary */ 340 uint16 reserved[3]; 341 /** always align on 8 byte boundary */ 342 bcm_addr64_t host_buf_addr; 343 uint32 rsvd[4]; 344 } ioctl_resp_evt_buf_post_msg_t; 345 346 /* buffer post messages for device to use to return dbg buffers */ 347 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t; 348 349 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024) 350 351 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024) 352 353 /* An infobuf host buffer starts with a 32 bit (LE) version. */ 354 #define PCIE_INFOBUF_V1 1 355 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that 356 * is wrapped previously/also in a WLC_E_TRACE event. See structure 357 * msgrace_hdr_t in msgtrace.h. 358 */ 359 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1 360 361 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that 362 * is wrapped previously/also in a WLC_E_TRACE event. See structure 363 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE 364 * and a LOGTRACE is the "trace type" field.) 365 */ 366 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2 367 368 /* An infobuf version 1 host buffer has a single TLV. The information on the 369 * version 1 types follow this structure definition. (int's LE) 370 */ 371 typedef struct info_buf_payload_hdr_s { 372 uint16 type; 373 uint16 length; 374 } info_buf_payload_hdr_t; 375 376 /* BT logs/memory to DMA directly from BT memory to host */ 377 typedef struct info_buf_btlog_s { 378 void (*status_cb)(void *ctx, void *p, int error); /* obsolete - to be removed */ 379 void *ctx; 380 dma64addr_t src_addr; 381 uint32 length; 382 bool (*pcie_status_cb)(osl_t *osh, void *p, int error); 383 uint32 bt_intstatus; 384 int error; 385 } info_buf_btlog_t; 386 387 /** snapshot upload request message */ 388 typedef struct snapshot_upload_request_msg { 389 /** common message header */ 390 cmn_msg_hdr_t cmn_hdr; 391 /** length of the snaphost buffer supplied */ 392 uint32 snapshot_buf_len; 393 /** type of snapshot */ 394 uint8 snapshot_type; 395 /** snapshot param */ 396 uint8 snapshot_param; 397 /** to align the host address on 8 byte boundary */ 398 uint8 reserved[2]; 399 /** always align on 8 byte boundary */ 400 bcm_addr64_t host_buf_addr; 401 uint32 rsvd[4]; 402 } snapshot_upload_request_msg_t; 403 404 /** snapshot types */ 405 typedef enum bcmpcie_snapshot_type { 406 SNAPSHOT_TYPE_BT = 0, /* Bluetooth SRAM and patch RAM */ 407 SNAPSHOT_TYPE_WLAN_SOCRAM = 1, /* WLAN SOCRAM */ 408 SNAPSHOT_TYPE_WLAN_HEAP = 2, /* WLAN HEAP */ 409 SNAPSHOT_TYPE_WLAN_REGISTER = 3 /* WLAN registers */ 410 } bcmpcie_snapshot_type_t; 411 412 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF 413 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2 414 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3 415 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0 416 417 typedef struct pcie_dma_xfer_params { 418 /** common message header */ 419 cmn_msg_hdr_t cmn_hdr; 420 421 /** always align on 8 byte boundary */ 422 bcm_addr64_t host_input_buf_addr; 423 424 /** always align on 8 byte boundary */ 425 bcm_addr64_t host_ouput_buf_addr; 426 427 /** length of transfer */ 428 uint32 xfer_len; 429 /** delay before doing the src txfer */ 430 uint32 srcdelay; 431 /** delay before doing the dest txfer */ 432 uint32 destdelay; 433 uint8 rsvd[3]; 434 /* bit0: D11 DMA loopback flag */ 435 uint8 flags; 436 } pcie_dma_xfer_params_t; 437 438 #define BCMPCIE_FLOW_RING_INTF_HP2P 0x1 439 /** Complete msgbuf hdr for flow ring update from host to dongle */ 440 typedef struct tx_flowring_create_request { 441 cmn_msg_hdr_t msg; 442 uint8 da[ETHER_ADDR_LEN]; 443 uint8 sa[ETHER_ADDR_LEN]; 444 uint8 tid; 445 uint8 if_flags; 446 uint16 flow_ring_id; 447 uint8 tc; 448 /* priority_ifrmmask is to define core mask in ifrm mode. 449 * currently it is not used for priority. so uses solely for ifrm mask 450 */ 451 uint8 priority_ifrmmask; 452 uint16 int_vector; 453 uint16 max_items; 454 uint16 len_item; 455 bcm_addr64_t flow_ring_ptr; 456 } tx_flowring_create_request_t; 457 458 typedef struct tx_flowring_delete_request { 459 cmn_msg_hdr_t msg; 460 uint16 flow_ring_id; 461 uint16 reason; 462 uint32 rsvd[7]; 463 } tx_flowring_delete_request_t; 464 465 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t; 466 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t; 467 468 typedef struct tx_flowring_flush_request { 469 cmn_msg_hdr_t msg; 470 uint16 flow_ring_id; 471 uint16 reason; 472 uint32 rsvd[7]; 473 } tx_flowring_flush_request_t; 474 475 /** Subtypes for ring_config_req control message */ 476 typedef enum ring_config_subtype { 477 /** Default D2H PCIE doorbell override using ring_config_req msg */ 478 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */ 479 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */ 480 } ring_config_subtype_t; 481 482 typedef struct ring_config_req { 483 cmn_msg_hdr_t msg; 484 uint16 subtype; 485 uint16 ring_id; 486 uint32 rsvd; 487 union { 488 uint32 data[6]; 489 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */ 490 bcmpcie_soft_doorbell_t soft_doorbell; 491 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */ 492 bcmpcie_msi_offset_config_t msi_offset; 493 }; 494 } ring_config_req_t; 495 496 /* data structure to use to create on the fly d2h rings */ 497 typedef struct d2h_ring_create_req { 498 cmn_msg_hdr_t msg; 499 uint16 ring_id; 500 uint16 ring_type; 501 uint32 flags; 502 bcm_addr64_t ring_ptr; 503 uint16 max_items; 504 uint16 len_item; 505 uint32 rsvd[3]; 506 } d2h_ring_create_req_t; 507 508 /* data structure to use to create on the fly h2d rings */ 509 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4 510 typedef struct h2d_ring_create_req { 511 cmn_msg_hdr_t msg; 512 uint16 ring_id; 513 uint8 ring_type; 514 uint8 n_completion_ids; 515 uint32 flags; 516 bcm_addr64_t ring_ptr; 517 uint16 max_items; 518 uint16 len_item; 519 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED]; 520 uint32 rsvd; 521 } h2d_ring_create_req_t; 522 523 typedef struct d2h_ring_config_req { 524 cmn_msg_hdr_t msg; 525 uint16 d2h_ring_config_subtype; 526 uint16 d2h_ring_id; 527 uint32 d2h_ring_config_data[4]; 528 uint32 rsvd[3]; 529 } d2h_ring_config_req_t; 530 531 typedef struct h2d_ring_config_req { 532 cmn_msg_hdr_t msg; 533 uint16 h2d_ring_config_subtype; 534 uint16 h2d_ring_id; 535 uint32 h2d_ring_config_data; 536 uint32 rsvd[6]; 537 } h2d_ring_config_req_t; 538 539 typedef struct h2d_mailbox_data { 540 cmn_msg_hdr_t msg; 541 uint32 mail_box_data; 542 uint32 rsvd[7]; 543 } h2d_mailbox_data_t; 544 typedef struct host_timestamp_msg { 545 cmn_msg_hdr_t msg; 546 uint16 xt_id; /* transaction ID */ 547 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */ 548 uint16 seqnum; /* number of times host captured the timestamp */ 549 uint16 rsvd; 550 /* always align on 8 byte boundary */ 551 bcm_addr64_t host_buf_addr; 552 /* rsvd */ 553 uint32 rsvd1[4]; 554 } host_timestamp_msg_t; 555 556 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */ 557 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t; 558 559 typedef union ctrl_submit_item { 560 ioctl_req_msg_t ioctl_req; 561 ioctl_resp_evt_buf_post_msg_t resp_buf_post; 562 pcie_dma_xfer_params_t dma_xfer; 563 tx_flowring_create_request_t flow_create; 564 tx_flowring_delete_request_t flow_delete; 565 tx_flowring_flush_request_t flow_flush; 566 ring_config_req_t ring_config_req; 567 d2h_ring_create_req_t d2h_create; 568 h2d_ring_create_req_t h2d_create; 569 d2h_ring_config_req_t d2h_config; 570 h2d_ring_config_req_t h2d_config; 571 h2d_mailbox_data_t h2d_mailbox_data; 572 host_timestamp_msg_t host_ts; 573 ts_buf_post_msg_t ts_buf_post; 574 d2h_ring_delete_req_t d2h_delete; 575 h2d_ring_delete_req_t h2d_delete; 576 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE]; 577 } ctrl_submit_item_t; 578 579 typedef struct info_ring_submit_item { 580 info_buf_post_msg_t info_buf_post; 581 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE]; 582 } info_sumbit_item_t; 583 584 /** Control Completion messages (20 bytes) */ 585 typedef struct compl_msg_hdr { 586 union { 587 /** status for the completion */ 588 int16 status; 589 590 /* mutually exclusive with pkt fate debug feature */ 591 struct pktts_compl_hdr { 592 uint16 d_t4; /* Delta TimeStamp 3: T4-tref */ 593 } tx_pktts; 594 }; 595 /** submisison flow ring id which generated this status */ 596 union { 597 uint16 ring_id; 598 uint16 flow_ring_id; 599 }; 600 } compl_msg_hdr_t; 601 602 /** XOR checksum or a magic number to audit DMA done */ 603 typedef uint32 dma_done_t; 604 605 #define MAX_CLKSRC_ID 0xF 606 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF 607 #define TX_PKT_RETRY_CNT_0_SHIFT 0 608 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00 609 #define TX_PKT_RETRY_CNT_1_SHIFT 8 610 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000 611 #define TX_PKT_RETRY_CNT_2_SHIFT 16 612 #define TX_PKT_BAND_INFO 0x0F000000 613 #define TX_PKT_BAND_INFO_SHIFT 24 614 #define TX_PKT_VALID_INFO 0xF0000000 615 #define TX_PKT_VALID_INFO_SHIFT 28 616 617 typedef struct ts_timestamp_srcid { 618 union { 619 uint32 ts_low; /* time stamp low 32 bits */ 620 uint32 rate_spec; /* use ratespec */ 621 }; 622 union { 623 uint32 ts_high; /* time stamp high 28 bits */ 624 union { 625 uint32 ts_high_ext :28; /* time stamp high 28 bits */ 626 uint32 clk_id_ext :3; /* clock ID source */ 627 uint32 phase :1; /* Phase bit */ 628 dma_done_t marker_ext; 629 }; 630 uint32 tx_pkt_band_retry_info; 631 }; 632 } ts_timestamp_srcid_t; 633 634 typedef ts_timestamp_srcid_t ipc_timestamp_t; 635 636 typedef struct ts_timestamp { 637 uint32 low; 638 uint32 high; 639 } ts_timestamp_t; 640 641 typedef ts_timestamp_t tick_count_64_t; 642 typedef ts_timestamp_t ts_timestamp_ns_64_t; 643 typedef ts_timestamp_t ts_correction_m_t; 644 typedef ts_timestamp_t ts_correction_b_t; 645 646 typedef struct _pktts { 647 uint32 tref; /* Ref Clk in uSec (currently, tsf) */ 648 uint16 d_t2; /* Delta TimeStamp 1: T2-tref */ 649 uint16 d_t3; /* Delta TimeStamp 2: T3-tref */ 650 } pktts_t; 651 652 /* completion header status codes */ 653 #define BCMPCIE_SUCCESS 0 654 #define BCMPCIE_NOTFOUND 1 655 #define BCMPCIE_NOMEM 2 656 #define BCMPCIE_BADOPTION 3 657 #define BCMPCIE_RING_IN_USE 4 658 #define BCMPCIE_RING_ID_INVALID 5 659 #define BCMPCIE_PKT_FLUSH 6 660 #define BCMPCIE_NO_EVENT_BUF 7 661 #define BCMPCIE_NO_RX_BUF 8 662 #define BCMPCIE_NO_IOCTLRESP_BUF 9 663 #define BCMPCIE_MAX_IOCTLRESP_BUF 10 664 #define BCMPCIE_MAX_EVENT_BUF 11 665 #define BCMPCIE_BAD_PHASE 12 666 #define BCMPCIE_INVALID_CPL_RINGID 13 667 #define BCMPCIE_RING_TYPE_INVALID 14 668 #define BCMPCIE_NO_TS_EVENT_BUF 15 669 #define BCMPCIE_MAX_TS_EVENT_BUF 16 670 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17 671 #define BCMPCIE_BT_DMA_ERR 18 672 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19 673 #define BCMPCIE_SNAPSHOT_ERR 20 674 #define BCMPCIE_NOT_READY 21 675 #define BCMPCIE_INVALID_DATA 22 676 #define BCMPCIE_NO_RESPONSE 23 677 #define BCMPCIE_NO_CLOCK 24 678 679 /** IOCTL completion response */ 680 typedef struct ioctl_compl_resp_msg { 681 /** common message header */ 682 cmn_msg_hdr_t cmn_hdr; 683 /** completion message header */ 684 compl_msg_hdr_t compl_hdr; 685 /** response buffer len where a host buffer is involved */ 686 uint16 resp_len; 687 /** transaction id to pair with a request */ 688 uint16 trans_id; 689 /** cmd id */ 690 uint32 cmd; 691 /** XOR checksum or a magic number to audit DMA done */ 692 dma_done_t marker; 693 } ioctl_comp_resp_msg_t; 694 695 /** IOCTL request acknowledgement */ 696 typedef struct ioctl_req_ack_msg { 697 /** common message header */ 698 cmn_msg_hdr_t cmn_hdr; 699 /** completion message header */ 700 compl_msg_hdr_t compl_hdr; 701 /** cmd id */ 702 uint32 cmd; 703 uint32 rsvd; 704 /** XOR checksum or a magic number to audit DMA done */ 705 dma_done_t marker; 706 } ioctl_req_ack_msg_t; 707 708 /** WL event message: send from device to host */ 709 typedef struct wlevent_req_msg { 710 /** common message header */ 711 cmn_msg_hdr_t cmn_hdr; 712 /** completion message header */ 713 compl_msg_hdr_t compl_hdr; 714 /** event data len valid with the event buffer */ 715 uint16 event_data_len; 716 /** sequence number */ 717 uint16 seqnum; 718 /** rsvd */ 719 uint32 rsvd; 720 /** XOR checksum or a magic number to audit DMA done */ 721 dma_done_t marker; 722 } wlevent_req_msg_t; 723 724 /** dma xfer complete message */ 725 typedef struct pcie_dmaxfer_cmplt { 726 /** common message header */ 727 cmn_msg_hdr_t cmn_hdr; 728 /** completion message header */ 729 compl_msg_hdr_t compl_hdr; 730 uint32 rsvd[2]; 731 /** XOR checksum or a magic number to audit DMA done */ 732 dma_done_t marker; 733 } pcie_dmaxfer_cmplt_t; 734 735 /** general status message */ 736 typedef struct pcie_gen_status { 737 /** common message header */ 738 cmn_msg_hdr_t cmn_hdr; 739 /** completion message header */ 740 compl_msg_hdr_t compl_hdr; 741 uint32 rsvd[2]; 742 /** XOR checksum or a magic number to audit DMA done */ 743 dma_done_t marker; 744 } pcie_gen_status_t; 745 746 /** ring status message */ 747 typedef struct pcie_ring_status { 748 /** common message header */ 749 cmn_msg_hdr_t cmn_hdr; 750 /** completion message header */ 751 compl_msg_hdr_t compl_hdr; 752 /** message which firmware couldn't decode */ 753 uint16 write_idx; 754 uint16 rsvd[3]; 755 /** XOR checksum or a magic number to audit DMA done */ 756 dma_done_t marker; 757 } pcie_ring_status_t; 758 759 typedef struct ring_create_response { 760 cmn_msg_hdr_t cmn_hdr; 761 compl_msg_hdr_t cmplt; 762 uint32 rsvd[2]; 763 /** XOR checksum or a magic number to audit DMA done */ 764 dma_done_t marker; 765 } ring_create_response_t; 766 767 typedef ring_create_response_t tx_flowring_create_response_t; 768 typedef ring_create_response_t h2d_ring_create_response_t; 769 typedef ring_create_response_t d2h_ring_create_response_t; 770 771 typedef struct tx_flowring_delete_response { 772 cmn_msg_hdr_t msg; 773 compl_msg_hdr_t cmplt; 774 uint16 read_idx; 775 uint16 rsvd[3]; 776 /** XOR checksum or a magic number to audit DMA done */ 777 dma_done_t marker; 778 } tx_flowring_delete_response_t; 779 780 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t; 781 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t; 782 783 typedef struct tx_flowring_flush_response { 784 cmn_msg_hdr_t msg; 785 compl_msg_hdr_t cmplt; 786 uint32 rsvd[2]; 787 /** XOR checksum or a magic number to audit DMA done */ 788 dma_done_t marker; 789 } tx_flowring_flush_response_t; 790 791 /** Common layout of all d2h control messages */ 792 typedef struct ctrl_compl_msg { 793 /** common message header */ 794 cmn_msg_hdr_t cmn_hdr; 795 /** completion message header */ 796 compl_msg_hdr_t compl_hdr; 797 uint32 rsvd[2]; 798 /** XOR checksum or a magic number to audit DMA done */ 799 dma_done_t marker; 800 } ctrl_compl_msg_t; 801 802 typedef struct ring_config_resp { 803 /** common message header */ 804 cmn_msg_hdr_t cmn_hdr; 805 /** completion message header */ 806 compl_msg_hdr_t compl_hdr; 807 uint16 subtype; 808 uint16 rsvd[3]; 809 /** XOR checksum or a magic number to audit DMA done */ 810 dma_done_t marker; 811 } ring_config_resp_t; 812 813 typedef struct d2h_mailbox_data { 814 cmn_msg_hdr_t msg; 815 compl_msg_hdr_t cmplt; 816 uint32 d2h_mailbox_data; 817 uint32 rsvd[1]; 818 /* XOR checksum or a magic number to audit DMA done */ 819 dma_done_t marker; 820 } d2h_mailbox_data_t; 821 822 /* dbg buf completion msg: send from device to host */ 823 typedef struct info_buf_resp { 824 /* common message header */ 825 cmn_msg_hdr_t cmn_hdr; 826 /* completion message header */ 827 compl_msg_hdr_t compl_hdr; 828 /* event data len valid with the event buffer */ 829 uint16 info_data_len; 830 /* sequence number */ 831 uint16 seqnum; 832 /* destination */ 833 uint8 dest; 834 /* rsvd */ 835 uint8 rsvd[3]; 836 /* XOR checksum or a magic number to audit DMA done */ 837 dma_done_t marker; 838 } info_buf_resp_t; 839 840 /* snapshot completion msg: send from device to host */ 841 typedef struct snapshot_resp { 842 /* common message header */ 843 cmn_msg_hdr_t cmn_hdr; 844 /* completion message header */ 845 compl_msg_hdr_t compl_hdr; 846 /* snapshot length uploaded */ 847 uint32 resp_len; 848 /* snapshot type */ 849 uint8 type; 850 /* rsvd */ 851 uint8 rsvd[3]; 852 /* XOR checksum or a magic number to audit DMA done */ 853 dma_done_t marker; 854 } snapshot_resp_t; 855 856 typedef struct info_ring_cpl_item { 857 info_buf_resp_t info_buf_post; 858 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE]; 859 } info_cpl_item_t; 860 861 typedef struct host_timestamp_msg_cpl { 862 cmn_msg_hdr_t msg; 863 compl_msg_hdr_t cmplt; 864 uint16 xt_id; /* transaction ID */ 865 uint16 rsvd; 866 uint32 rsvd1; 867 /* XOR checksum or a magic number to audit DMA done */ 868 dma_done_t marker; 869 } host_timestamp_msg_cpl_t; 870 871 typedef struct fw_timestamp_event_msg { 872 cmn_msg_hdr_t msg; 873 compl_msg_hdr_t cmplt; 874 /* fw captures time stamp info and passed that to host in TLVs */ 875 uint16 buf_len; /* length of the time stamp data copied in host buf */ 876 uint16 seqnum; /* number of times fw captured time stamp */ 877 uint32 rsvd; 878 /* XOR checksum or a magic number to audit DMA done */ 879 dma_done_t marker; 880 } fw_timestamp_event_msg_t; 881 882 typedef union ctrl_completion_item { 883 ioctl_comp_resp_msg_t ioctl_resp; 884 wlevent_req_msg_t event; 885 ioctl_req_ack_msg_t ioct_ack; 886 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt; 887 pcie_gen_status_t pcie_gen_status; 888 pcie_ring_status_t pcie_ring_status; 889 tx_flowring_create_response_t txfl_create_resp; 890 tx_flowring_delete_response_t txfl_delete_resp; 891 tx_flowring_flush_response_t txfl_flush_resp; 892 ctrl_compl_msg_t ctrl_compl; 893 ring_config_resp_t ring_config_resp; 894 d2h_mailbox_data_t d2h_mailbox_data; 895 info_buf_resp_t dbg_resp; 896 h2d_ring_create_response_t h2d_ring_create_resp; 897 d2h_ring_create_response_t d2h_ring_create_resp; 898 host_timestamp_msg_cpl_t host_ts_cpl; 899 fw_timestamp_event_msg_t fw_ts_event; 900 h2d_ring_delete_response_t h2d_ring_delete_resp; 901 d2h_ring_delete_response_t d2h_ring_delete_resp; 902 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE]; 903 } ctrl_completion_item_t; 904 905 /** H2D Rxpost ring work items */ 906 typedef struct host_rxbuf_post { 907 /** common message header */ 908 cmn_msg_hdr_t cmn_hdr; 909 /** provided meta data buffer len */ 910 uint16 metadata_buf_len; 911 /** provided data buffer len to receive data */ 912 uint16 data_buf_len; 913 /** alignment to make the host buffers start on 8 byte boundary */ 914 uint32 rsvd; 915 /** provided meta data buffer */ 916 bcm_addr64_t metadata_buf_addr; 917 /** provided data buffer to receive data */ 918 bcm_addr64_t data_buf_addr; 919 } host_rxbuf_post_t; 920 921 typedef union rxbuf_submit_item { 922 host_rxbuf_post_t rxpost; 923 unsigned char check[H2DRING_RXPOST_ITEMSIZE]; 924 } rxbuf_submit_item_t; 925 926 /* D2H Rxcompletion ring work items for IPC rev7 */ 927 typedef struct host_rxbuf_cmpl { 928 /** common message header */ 929 cmn_msg_hdr_t cmn_hdr; 930 /** completion message header */ 931 compl_msg_hdr_t compl_hdr; 932 /** filled up meta data len */ 933 uint16 metadata_len; 934 /** filled up buffer len to receive data */ 935 uint16 data_len; 936 /** offset in the host rx buffer where the data starts */ 937 uint16 data_offset; 938 /** offset in the host rx buffer where the data starts */ 939 uint16 flags; 940 /** rx status */ 941 uint32 rx_status_0; 942 uint32 rx_status_1; 943 944 union { /* size per IPC = (3 x uint32) bytes */ 945 struct { 946 /* used by Monitor mode */ 947 uint32 marker; 948 /* timestamp */ 949 ipc_timestamp_t ts; 950 }; 951 952 /* LatTS_With_XORCSUM */ 953 struct { 954 /* latency timestamp */ 955 pktts_t rx_pktts; 956 /* XOR checksum or a magic number to audit DMA done */ 957 dma_done_t marker_ext; 958 }; 959 }; 960 } host_rxbuf_cmpl_t; 961 962 typedef union rxbuf_complete_item { 963 host_rxbuf_cmpl_t rxcmpl; 964 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE]; 965 } rxbuf_complete_item_t; 966 967 typedef struct host_txbuf_post { 968 /** common message header */ 969 cmn_msg_hdr_t cmn_hdr; 970 /** eth header */ 971 uint8 txhdr[ETHER_HDR_LEN]; 972 /** flags */ 973 uint8 flags; 974 /** number of segments */ 975 uint8 seg_cnt; 976 977 /** provided meta data buffer for txstatus */ 978 bcm_addr64_t metadata_buf_addr; 979 /** provided data buffer to receive data */ 980 bcm_addr64_t data_buf_addr; 981 /** provided meta data buffer len */ 982 uint16 metadata_buf_len; 983 /** provided data buffer len to receive data */ 984 uint16 data_len; 985 union { 986 struct { 987 /** extended transmit flags */ 988 uint8 ext_flags; 989 uint8 scale_factor; 990 991 /** user defined rate */ 992 uint8 rate; 993 uint8 exp_time; 994 }; 995 /** XOR checksum or a magic number to audit DMA done */ 996 dma_done_t marker; 997 }; 998 } host_txbuf_post_t; 999 1000 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01 1001 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02 1002 1003 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */ 1004 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR 0x02 /* Disable aggregation for this frame */ 1005 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame */ 1006 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */ 1007 1008 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */ 1009 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */ 1010 1011 #define BCMPCIE_PKT_FLAGS_EPOCH_SHIFT 3u 1012 #define BCMPCIE_PKT_FLAGS_EPOCH_MASK (1u << BCMPCIE_PKT_FLAGS_EPOCH_SHIFT) 1013 1014 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5 1015 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT) 1016 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00 1017 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01 1018 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02 1019 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03 1020 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8 1021 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT) 1022 1023 /* These are added to fix up compile issues */ 1024 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3 1025 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11 1026 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT 1027 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK 1028 1029 /* H2D Txpost ring work items */ 1030 typedef union txbuf_submit_item { 1031 host_txbuf_post_t txpost; 1032 unsigned char check[H2DRING_TXPOST_ITEMSIZE]; 1033 } txbuf_submit_item_t; 1034 1035 /* D2H Txcompletion ring work items - extended for IOC rev7 */ 1036 typedef struct host_txbuf_cmpl { 1037 /** common message header */ 1038 cmn_msg_hdr_t cmn_hdr; 1039 /** completion message header */ 1040 compl_msg_hdr_t compl_hdr; 1041 1042 union { /* size per IPC = (3 x uint32) bytes */ 1043 /* Usage 1: TxS_With_TimeSync */ 1044 struct { 1045 struct { 1046 union { 1047 /** provided meta data len */ 1048 uint16 metadata_len; 1049 /** provided extended TX status */ 1050 uint16 tx_status_ext; 1051 }; /*Ext_TxStatus */ 1052 1053 /** WLAN side txstatus */ 1054 uint16 tx_status; 1055 }; /* TxS */ 1056 /* timestamp */ 1057 ipc_timestamp_t ts; 1058 }; /* TxS_with_TS */ 1059 1060 /* Usage 2: LatTS_With_XORCSUM */ 1061 struct { 1062 /* latency timestamp */ 1063 pktts_t tx_pktts; 1064 /* XOR checksum or a magic number to audit DMA done */ 1065 dma_done_t marker_ext; 1066 }; 1067 }; 1068 1069 } host_txbuf_cmpl_t; 1070 1071 typedef union txbuf_complete_item { 1072 host_txbuf_cmpl_t txcmpl; 1073 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE]; 1074 } txbuf_complete_item_t; 1075 1076 #define PCIE_METADATA_VER 1u 1077 1078 /* version and length are not part of this structure. 1079 * dhd queries version and length through bus iovar "bus:metadata_info". 1080 */ 1081 struct metadata_txcmpl_v1 { 1082 uint32 tref; /* TSF or Ref Clock in uSecs */ 1083 uint16 d_t2; /* T2-fwt1 delta */ 1084 uint16 d_t3; /* T3-fwt1 delta */ 1085 uint16 d_t4; /* T4-fwt1 delta */ 1086 uint16 rsvd; /* reserved */ 1087 }; 1088 typedef struct metadata_txcmpl_v1 metadata_txcmpl_t; 1089 1090 #define BCMPCIE_D2H_METADATA_HDRLEN 4 1091 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4) 1092 1093 /** ret buf struct */ 1094 typedef struct ret_buf_ptr { 1095 uint32 low_addr; 1096 uint32 high_addr; 1097 } ret_buf_t; 1098 1099 #ifdef PCIE_API_REV1 1100 1101 /* ioctl specific hdr */ 1102 typedef struct ioctl_hdr { 1103 uint16 cmd; 1104 uint16 retbuf_len; 1105 uint32 cmd_id; 1106 } ioctl_hdr_t; 1107 1108 typedef struct ioctlptr_hdr { 1109 uint16 cmd; 1110 uint16 retbuf_len; 1111 uint16 buflen; 1112 uint16 rsvd; 1113 uint32 cmd_id; 1114 } ioctlptr_hdr_t; 1115 1116 #else /* PCIE_API_REV1 */ 1117 1118 typedef struct ioctl_req_hdr { 1119 uint32 pkt_id; /**< Packet ID */ 1120 uint32 cmd; /**< IOCTL ID */ 1121 uint16 retbuf_len; 1122 uint16 buflen; 1123 uint16 xt_id; /**< transaction ID */ 1124 uint16 rsvd[1]; 1125 } ioctl_req_hdr_t; 1126 1127 #endif /* PCIE_API_REV1 */ 1128 1129 /** Complete msgbuf hdr for ioctl from host to dongle */ 1130 typedef struct ioct_reqst_hdr { 1131 cmn_msg_hdr_t msg; 1132 #ifdef PCIE_API_REV1 1133 ioctl_hdr_t ioct_hdr; 1134 #else 1135 ioctl_req_hdr_t ioct_hdr; 1136 #endif // endif 1137 ret_buf_t ret_buf; 1138 } ioct_reqst_hdr_t; 1139 1140 typedef struct ioctptr_reqst_hdr { 1141 cmn_msg_hdr_t msg; 1142 #ifdef PCIE_API_REV1 1143 ioctlptr_hdr_t ioct_hdr; 1144 #else 1145 ioctl_req_hdr_t ioct_hdr; 1146 #endif // endif 1147 ret_buf_t ret_buf; 1148 ret_buf_t ioct_buf; 1149 } ioctptr_reqst_hdr_t; 1150 1151 /** ioctl response header */ 1152 typedef struct ioct_resp_hdr { 1153 cmn_msg_hdr_t msg; 1154 #ifdef PCIE_API_REV1 1155 uint32 cmd_id; 1156 #else 1157 uint32 pkt_id; 1158 #endif // endif 1159 uint32 status; 1160 uint32 ret_len; 1161 uint32 inline_data; 1162 #ifdef PCIE_API_REV1 1163 #else 1164 uint16 xt_id; /**< transaction ID */ 1165 uint16 rsvd[1]; 1166 #endif // endif 1167 } ioct_resp_hdr_t; 1168 1169 /* ioct resp header used in dongle */ 1170 /* ret buf hdr will be stripped off inside dongle itself */ 1171 typedef struct msgbuf_ioctl_resp { 1172 ioct_resp_hdr_t ioct_hdr; 1173 ret_buf_t ret_buf; /**< ret buf pointers */ 1174 } msgbuf_ioct_resp_t; 1175 1176 /** WL event hdr info */ 1177 typedef struct wl_event_hdr { 1178 cmn_msg_hdr_t msg; 1179 uint16 event; 1180 uint8 flags; 1181 uint8 rsvd; 1182 uint16 retbuf_len; 1183 uint16 rsvd1; 1184 uint32 rxbufid; 1185 } wl_event_hdr_t; 1186 1187 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF 1188 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE 1189 1190 typedef struct txbatch_lenptr_tup { 1191 uint32 pktid; 1192 uint16 pktlen; 1193 uint16 rsvd; 1194 ret_buf_t ret_buf; /**< ret buf pointers */ 1195 } txbatch_lenptr_tup_t; 1196 1197 typedef struct txbatch_cmn_msghdr { 1198 cmn_msg_hdr_t msg; 1199 uint8 priority; 1200 uint8 hdrlen; 1201 uint8 pktcnt; 1202 uint8 flowid; 1203 uint8 txhdr[ETHER_HDR_LEN]; 1204 uint16 rsvd; 1205 } txbatch_cmn_msghdr_t; 1206 1207 typedef struct txbatch_msghdr { 1208 txbatch_cmn_msghdr_t txcmn; 1209 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */ 1210 } txbatch_msghdr_t; 1211 1212 /* TX desc posting header */ 1213 typedef struct tx_lenptr_tup { 1214 uint16 pktlen; 1215 uint16 rsvd; 1216 ret_buf_t ret_buf; /**< ret buf pointers */ 1217 } tx_lenptr_tup_t; 1218 1219 typedef struct txdescr_cmn_msghdr { 1220 cmn_msg_hdr_t msg; 1221 uint8 priority; 1222 uint8 hdrlen; 1223 uint8 descrcnt; 1224 uint8 flowid; 1225 uint32 pktid; 1226 } txdescr_cmn_msghdr_t; 1227 1228 typedef struct txdescr_msghdr { 1229 txdescr_cmn_msghdr_t txcmn; 1230 uint8 txhdr[ETHER_HDR_LEN]; 1231 uint16 rsvd; 1232 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */ 1233 } txdescr_msghdr_t; 1234 1235 /** Tx status header info */ 1236 typedef struct txstatus_hdr { 1237 cmn_msg_hdr_t msg; 1238 uint32 pktid; 1239 } txstatus_hdr_t; 1240 1241 /** RX bufid-len-ptr tuple */ 1242 typedef struct rx_lenptr_tup { 1243 uint32 rxbufid; 1244 uint16 len; 1245 uint16 rsvd2; 1246 ret_buf_t ret_buf; /**< ret buf pointers */ 1247 } rx_lenptr_tup_t; 1248 1249 /** Rx descr Post hdr info */ 1250 typedef struct rxdesc_msghdr { 1251 cmn_msg_hdr_t msg; 1252 uint16 rsvd0; 1253 uint8 rsvd1; 1254 uint8 descnt; 1255 rx_lenptr_tup_t rx_tup[0]; 1256 } rxdesc_msghdr_t; 1257 1258 /** RX complete tuples */ 1259 typedef struct rxcmplt_tup { 1260 uint16 retbuf_len; 1261 uint16 data_offset; 1262 uint32 rxstatus0; 1263 uint32 rxstatus1; 1264 uint32 rxbufid; 1265 } rxcmplt_tup_t; 1266 1267 /** RX complete messge hdr */ 1268 typedef struct rxcmplt_hdr { 1269 cmn_msg_hdr_t msg; 1270 uint16 rsvd0; 1271 uint16 rxcmpltcnt; 1272 rxcmplt_tup_t rx_tup[0]; 1273 } rxcmplt_hdr_t; 1274 1275 typedef struct hostevent_hdr { 1276 cmn_msg_hdr_t msg; 1277 uint32 evnt_pyld; 1278 } hostevent_hdr_t; 1279 1280 typedef struct dma_xfer_params { 1281 uint32 src_physaddr_hi; 1282 uint32 src_physaddr_lo; 1283 uint32 dest_physaddr_hi; 1284 uint32 dest_physaddr_lo; 1285 uint32 len; 1286 uint32 srcdelay; 1287 uint32 destdelay; 1288 } dma_xfer_params_t; 1289 1290 enum { 1291 HOST_EVENT_CONS_CMD = 1 1292 }; 1293 1294 /* defines for flags */ 1295 #define MSGBUF_IOC_ACTION_MASK 0x1 1296 1297 #define MAX_SUSPEND_REQ 15 1298 1299 typedef struct tx_idle_flowring_suspend_request { 1300 cmn_msg_hdr_t msg; 1301 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */ 1302 uint16 num; /* number of flowid's to suspend */ 1303 } tx_idle_flowring_suspend_request_t; 1304 1305 typedef struct tx_idle_flowring_suspend_response { 1306 cmn_msg_hdr_t msg; 1307 compl_msg_hdr_t cmplt; 1308 uint32 rsvd[2]; 1309 dma_done_t marker; 1310 } tx_idle_flowring_suspend_response_t; 1311 1312 typedef struct tx_idle_flowring_resume_request { 1313 cmn_msg_hdr_t msg; 1314 uint16 flow_ring_id; 1315 uint16 reason; 1316 uint32 rsvd[7]; 1317 } tx_idle_flowring_resume_request_t; 1318 1319 typedef struct tx_idle_flowring_resume_response { 1320 cmn_msg_hdr_t msg; 1321 compl_msg_hdr_t cmplt; 1322 uint32 rsvd[2]; 1323 dma_done_t marker; 1324 } tx_idle_flowring_resume_response_t; 1325 1326 /* timesync related additions */ 1327 1328 typedef struct _bcm_xtlv { 1329 uint16 id; /* TLV idenitifier */ 1330 uint16 len; /* TLV length in bytes */ 1331 } _bcm_xtlv_t; 1332 1333 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0 1334 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1 1335 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2 1336 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3 1337 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4 1338 #define BCMMSGBUF_MAX_TSYNC_TAG 5 1339 1340 /* Flags in fw clock info TLV */ 1341 #define CAP_DEVICE_TS (1 << 0) 1342 #define CAP_CORRECTED_TS (1 << 1) 1343 #define TS_CLK_ACTIVE (1 << 2) 1344 1345 typedef struct ts_fw_clock_info { 1346 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */ 1347 ts_timestamp_srcid_t ts; /* tick count */ 1348 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */ 1349 uint32 nominal_clock_freq; 1350 uint32 reset_cnt; 1351 uint8 flags; 1352 uint8 rsvd[3]; 1353 } ts_fw_clock_info_t; 1354 1355 typedef struct ts_host_clock_info { 1356 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1357 tick_count_64_t ticks; /* 64 bit host tick counter */ 1358 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */ 1359 } ts_host_clock_info_t; 1360 1361 typedef struct ts_host_clock_sel { 1362 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */ 1363 uint32 seqnum; /* number of times GPIO time sync toggled */ 1364 uint8 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1365 uint8 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1366 uint16 rsvd[1]; 1367 } ts_host_clock_sel_t; 1368 1369 typedef struct ts_d2h_clock_correction { 1370 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1371 uint8 clk_id; /* clock source in the device */ 1372 uint8 rsvd[3]; 1373 ts_correction_m_t m; /* y = 'm' x + b */ 1374 ts_correction_b_t b; /* y = 'm' x + 'c' */ 1375 } ts_d2h_clock_correction_t; 1376 1377 typedef struct ts_host_timestamping_config { 1378 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */ 1379 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */ 1380 uint16 period_ms; 1381 uint8 flags; 1382 uint8 post_delay; 1383 uint32 reset_cnt; 1384 } ts_host_timestamping_config_t; 1385 1386 /* Flags in host timestamping config TLV */ 1387 #define FLAG_HOST_RESET (1 << 0) 1388 #define IS_HOST_RESET(x) ((x) & FLAG_HOST_RESET) 1389 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET) 1390 1391 #define FLAG_CONFIG_NODROP (1 << 1) 1392 #define IS_CONFIG_NODROP(x) ((x) & FLAG_CONFIG_NODROP) 1393 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP) 1394 1395 #endif /* _bcmmsgbuf_h_ */ 1396