1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Broadcom SDIO/PCMCIA 4 * Software-specific definitions shared between device and host side 5 * 6 * Copyright (C) 1999-2019, Broadcom. 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: bcmsdpcm.h 700076 2017-05-17 14:42:22Z $ 30 */ 31 32 #ifndef _bcmsdpcm_h_ 33 #define _bcmsdpcm_h_ 34 35 /* 36 * Software allocation of To SB Mailbox resources 37 */ 38 39 /* intstatus bits */ 40 #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ 41 #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ 42 #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ 43 #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ 44 45 #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 46 47 /* tosbmailbox bits corresponding to intstatus bits */ 48 #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ 49 #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ 50 #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ 51 #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ 52 #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ 53 54 /* tosbmailboxdata */ 55 56 #ifdef DS_PROT 57 /* Bit msgs for custom deep sleep protocol */ 58 #define SMB_DATA_D3INFORM 0x100 /* host announcing D3 entry */ 59 #define SMB_DATA_DSACK 0x200 /* host acking a deepsleep request */ 60 #define SMB_DATA_DSNACK 0x400 /* host nacking a deepsleep request */ 61 #endif /* DS_PROT */ 62 /* force a trap */ 63 #define SMB_DATA_TRAP 0x800 /* host forcing trap */ 64 65 #define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */ 66 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */ 67 68 /* 69 * Software allocation of To Host Mailbox resources 70 */ 71 72 /* intstatus bits */ 73 #define I_HMB_INT_ACK I_HMB_SW0 /* To Host Mailbox Dev Interrupt ACK */ 74 #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ 75 #define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ 76 #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ 77 #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ 78 79 #define I_TOHOSTMAIL (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT) 80 81 /* tohostmailbox bits corresponding to intstatus bits */ 82 #define HMB_INT_ACK (1 << 0) /* To Host Mailbox Dev Interrupt ACK */ 83 #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ 84 #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ 85 #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ 86 87 /* tohostmailboxdata */ 88 #define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */ 89 #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */ 90 #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ 91 #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ 92 #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ 93 94 #ifdef DS_PROT 95 /* Bit msgs for custom deep sleep protocol */ 96 #define HMB_DATA_DSREQ 0x100 /* firmware requesting deepsleep entry */ 97 #define HMB_DATA_DSEXIT 0x200 /* firmware announcing deepsleep exit */ 98 #define HMB_DATA_D3ACK 0x400 /* firmware acking a D3 notice from host */ 99 #define HMB_DATA_D3EXIT 0x800 /* firmware announcing D3 exit */ 100 #define HMB_DATA_DSPROT_MASK 0xf00 101 #endif /* DS_PROT */ 102 103 #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ 104 #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 105 106 #define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */ 107 #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */ 108 109 /* 110 * Software-defined protocol header 111 */ 112 113 /* Current protocol version */ 114 #define SDPCM_PROT_VERSION 4 115 116 /* SW frame header */ 117 #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 118 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 119 120 #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 121 #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 122 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 123 124 #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ 125 #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ 126 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 127 128 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */ 129 #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ 130 #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ 131 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ 132 #define SDPCM_NEXTLEN_OFFSET 2 133 134 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 135 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 136 #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 137 #define SDPCM_DOFFSET_MASK 0xff000000 138 #define SDPCM_DOFFSET_SHIFT 24 139 140 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 141 #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff) 142 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 143 #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 144 #define SDPCM_VERSION_OFFSET 6 /* Version # */ 145 #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) 146 #define SDPCM_UNUSED_OFFSET 7 /* Spare */ 147 #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) 148 149 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 150 151 /* logical channel numbers */ 152 #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 153 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 154 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 155 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ 156 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 157 #define SDPCM_MAX_CHANNEL 15 158 159 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */ 160 161 #define SDPCM_FLAG_RESVD0 0x01 162 #define SDPCM_FLAG_RESVD1 0x02 163 #define SDPCM_FLAG_GSPI_TXENAB 0x04 164 #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ 165 166 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ 167 #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) 168 169 #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) 170 171 /* For TEST_CHANNEL packets, define another 4-byte header */ 172 #define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); 173 * Semantics of Ext byte depend on command. 174 * Len is current or requested frame length, not 175 * including test header; sent little-endian. 176 */ 177 #define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */ 178 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 179 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 180 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 181 #define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count 182 * (Backward compatabilty) Set frame count in a 183 * 4 byte filed adjacent to the HDR 184 */ 185 #define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off 186 * Set frame count in a 4 byte filed adjacent to 187 * the HDR 188 */ 189 190 /* Handy macro for filling in datagen packets with a pattern */ 191 #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 192 193 /* 194 * Software counters (first part matches hardware counters) 195 */ 196 197 typedef volatile struct { 198 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 199 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 200 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 201 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 202 uint32 abort; /* AbortCount, SDIO: aborts */ 203 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 204 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 205 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 206 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 207 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 208 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 209 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 210 uint32 rxdescuflo; /* receive descriptor underflows */ 211 uint32 rxfifooflo; /* receive fifo overflows */ 212 uint32 txfifouflo; /* transmit fifo underflows */ 213 uint32 runt; /* runt (too short) frames recv'd from bus */ 214 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 215 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 216 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 217 uint32 rxfcrc; /* frame rx header indicates crc error */ 218 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 219 uint32 rxfwft; /* frame rx header indicates write frame termination */ 220 uint32 rxfabort; /* frame rx header indicates frame aborted */ 221 uint32 woosint; /* write out of sync interrupt */ 222 uint32 roosint; /* read out of sync interrupt */ 223 uint32 rftermint; /* read frame terminate interrupt */ 224 uint32 wftermint; /* write frame terminate interrupt */ 225 } sdpcmd_cnt_t; 226 227 /* 228 * Register Access Macros 229 */ 230 231 #define SDIODREV_IS(var, val) ((var) == (val)) 232 #define SDIODREV_GE(var, val) ((var) >= (val)) 233 #define SDIODREV_GT(var, val) ((var) > (val)) 234 #define SDIODREV_LT(var, val) ((var) < (val)) 235 #define SDIODREV_LE(var, val) ((var) <= (val)) 236 237 #define SDIODDMAREG32(h, dir, chnl) \ 238 ((dir) == DMA_TX ? \ 239 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \ 240 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) 241 242 #define SDIODDMAREG64(h, dir, chnl) \ 243 ((dir) == DMA_TX ? \ 244 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \ 245 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) 246 247 #define SDIODDMAREG(h, dir, chnl) \ 248 (SDIODREV_LT((h)->corerev, 1) ? \ 249 SDIODDMAREG32((h), (dir), (chnl)) : \ 250 SDIODDMAREG64((h), (dir), (chnl))) 251 252 #define PCMDDMAREG(h, dir, chnl) \ 253 ((dir) == DMA_TX ? \ 254 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \ 255 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv)) 256 257 #define SDPCMDMAREG(h, dir, chnl, coreid) \ 258 ((coreid) == SDIOD_CORE_ID ? \ 259 SDIODDMAREG(h, dir, chnl) : \ 260 PCMDDMAREG(h, dir, chnl)) 261 262 #define SDIODFIFOREG(h, corerev) \ 263 (SDIODREV_LT((corerev), 1) ? \ 264 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \ 265 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo))) 266 267 #define PCMDFIFOREG(h) \ 268 ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo)) 269 270 #define SDPCMFIFOREG(h, coreid, corerev) \ 271 ((coreid) == SDIOD_CORE_ID ? \ 272 SDIODFIFOREG(h, corerev) : \ 273 PCMDFIFOREG(h)) 274 275 /* 276 * Shared structure between dongle and the host. 277 * The structure contains pointers to trap or assert information. 278 */ 279 #define SDPCM_SHARED_VERSION 0x0001 280 #define SDPCM_SHARED_VERSION_MASK 0x00FF 281 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 282 #define SDPCM_SHARED_ASSERT 0x0200 283 #define SDPCM_SHARED_TRAP 0x0400 284 #define SDPCM_SHARED_IN_BRPT 0x0800 285 #define SDPCM_SHARED_SET_BRPT 0x1000 286 #define SDPCM_SHARED_PENDING_BRPT 0x2000 287 #define SDPCM_SHARED_FATAL_LOGBUF_VALID 0x100000 288 #define SDPCM_SHARED_RXLIM_POST 0x4000 289 #define SDPCM_SHARED_TXSEQ_SYNC 0x4000 290 291 typedef struct { 292 uint32 flags; 293 uint32 trap_addr; 294 uint32 assert_exp_addr; 295 uint32 assert_file_addr; 296 uint32 assert_line; 297 uint32 console_addr; /* Address of hnd_cons_t */ 298 uint32 msgtrace_addr; 299 uint32 fwid; 300 uint32 device_fatal_logbuf_start; 301 #ifdef BCMSDIO_TXSEQ_SYNC 302 uint32 txseq_sync_addr; 303 #endif /* BCMSDIO_TXSEQ_SYNC */ 304 } sdpcm_shared_t; 305 306 /* Device F/W provides the following access function: 307 * sdpcm_shared_t *hnd_get_sdpcm_shared(void); 308 */ 309 310 #endif /* _bcmsdpcm_h_ */ 311