1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SROM format definition. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: bcmsrom_fmt.h 688657 2017-03-07 10:12:56Z $ 29 */ 30 31 #ifndef _bcmsrom_fmt_h_ 32 #define _bcmsrom_fmt_h_ 33 34 #define SROM_MAXREV 16 /* max revision supported by driver */ 35 36 /* Maximum srom: 16 Kilobits == 2048 bytes */ 37 38 #define SROM_MAX 2048 39 #define SROM_MAXW 1024 40 41 #ifdef LARGE_NVRAM_MAXSZ 42 #define VARS_MAX LARGE_NVRAM_MAXSZ 43 #else 44 #define LARGE_NVRAM_MAXSZ 8192 45 #define VARS_MAX LARGE_NVRAM_MAXSZ 46 #endif /* LARGE_NVRAM_MAXSZ */ 47 48 /* PCI fields */ 49 #define PCI_F0DEVID 48 50 51 #define SROM_WORDS 64 52 #define SROM_SIGN_MINWORDS 128 53 #define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 54 55 #define SROM_SSID 2 56 #define SROM_SVID 3 57 58 #define SROM_WL1LHMAXP 29 59 60 #define SROM_WL1LPAB0 30 61 #define SROM_WL1LPAB1 31 62 #define SROM_WL1LPAB2 32 63 64 #define SROM_WL1HPAB0 33 65 #define SROM_WL1HPAB1 34 66 #define SROM_WL1HPAB2 35 67 68 #define SROM_MACHI_IL0 36 69 #define SROM_MACMID_IL0 37 70 #define SROM_MACLO_IL0 38 71 #define SROM_MACHI_ET0 39 72 #define SROM_MACMID_ET0 40 73 #define SROM_MACLO_ET0 41 74 #define SROM_MACHI_ET1 42 75 #define SROM_MACMID_ET1 43 76 #define SROM_MACLO_ET1 44 77 #define SROM3_MACHI 37 78 #define SROM3_MACMID 38 79 #define SROM3_MACLO 39 80 81 #define SROM_BXARSSI2G 40 82 #define SROM_BXARSSI5G 41 83 84 #define SROM_TRI52G 42 85 #define SROM_TRI5GHL 43 86 87 #define SROM_RXPO52G 45 88 89 #define SROM2_ENETPHY 45 90 91 #define SROM_AABREV 46 92 /* Fields in AABREV */ 93 #define SROM_BR_MASK 0x00ff 94 #define SROM_CC_MASK 0x0f00 95 #define SROM_CC_SHIFT 8 96 #define SROM_AA0_MASK 0x3000 97 #define SROM_AA0_SHIFT 12 98 #define SROM_AA1_MASK 0xc000 99 #define SROM_AA1_SHIFT 14 100 101 #define SROM_WL0PAB0 47 102 #define SROM_WL0PAB1 48 103 #define SROM_WL0PAB2 49 104 105 #define SROM_LEDBH10 50 106 #define SROM_LEDBH32 51 107 108 #define SROM_WL10MAXP 52 109 110 #define SROM_WL1PAB0 53 111 #define SROM_WL1PAB1 54 112 #define SROM_WL1PAB2 55 113 114 #define SROM_ITT 56 115 116 #define SROM_BFL 57 117 #define SROM_BFL2 28 118 #define SROM3_BFL2 61 119 120 #define SROM_AG10 58 121 122 #define SROM_CCODE 59 123 124 #define SROM_OPO 60 125 126 #define SROM3_LEDDC 62 127 128 #define SROM_CRCREV 63 129 130 /* SROM Rev 4: Reallocate the software part of the srom to accomodate 131 * MIMO features. It assumes up to two PCIE functions and 440 bytes 132 * of useable srom i.e. the useable storage in chips with OTP that 133 * implements hardware redundancy. 134 */ 135 136 #define SROM4_WORDS 220 137 138 #define SROM4_SIGN 32 139 #define SROM4_SIGNATURE 0x5372 140 141 #define SROM4_BREV 33 142 143 #define SROM4_BFL0 34 144 #define SROM4_BFL1 35 145 #define SROM4_BFL2 36 146 #define SROM4_BFL3 37 147 #define SROM5_BFL0 37 148 #define SROM5_BFL1 38 149 #define SROM5_BFL2 39 150 #define SROM5_BFL3 40 151 152 #define SROM4_MACHI 38 153 #define SROM4_MACMID 39 154 #define SROM4_MACLO 40 155 #define SROM5_MACHI 41 156 #define SROM5_MACMID 42 157 #define SROM5_MACLO 43 158 159 #define SROM4_CCODE 41 160 #define SROM4_REGREV 42 161 #define SROM5_CCODE 34 162 #define SROM5_REGREV 35 163 164 #define SROM4_LEDBH10 43 165 #define SROM4_LEDBH32 44 166 #define SROM5_LEDBH10 59 167 #define SROM5_LEDBH32 60 168 169 #define SROM4_LEDDC 45 170 #define SROM5_LEDDC 45 171 172 #define SROM4_AA 46 173 #define SROM4_AA2G_MASK 0x00ff 174 #define SROM4_AA2G_SHIFT 0 175 #define SROM4_AA5G_MASK 0xff00 176 #define SROM4_AA5G_SHIFT 8 177 178 #define SROM4_AG10 47 179 #define SROM4_AG32 48 180 181 #define SROM4_TXPID2G 49 182 #define SROM4_TXPID5G 51 183 #define SROM4_TXPID5GL 53 184 #define SROM4_TXPID5GH 55 185 186 #define SROM4_TXRXC 61 187 #define SROM4_TXCHAIN_MASK 0x000f 188 #define SROM4_TXCHAIN_SHIFT 0 189 #define SROM4_RXCHAIN_MASK 0x00f0 190 #define SROM4_RXCHAIN_SHIFT 4 191 #define SROM4_SWITCH_MASK 0xff00 192 #define SROM4_SWITCH_SHIFT 8 193 194 /* Per-path fields */ 195 #define MAX_PATH_SROM 4 196 #define SROM4_PATH0 64 197 #define SROM4_PATH1 87 198 #define SROM4_PATH2 110 199 #define SROM4_PATH3 133 200 201 #define SROM4_2G_ITT_MAXP 0 202 #define SROM4_2G_PA 1 203 #define SROM4_5G_ITT_MAXP 5 204 #define SROM4_5GLH_MAXP 6 205 #define SROM4_5G_PA 7 206 #define SROM4_5GL_PA 11 207 #define SROM4_5GH_PA 15 208 209 /* Fields in the ITT_MAXP and 5GLH_MAXP words */ 210 #define B2G_MAXP_MASK 0xff 211 #define B2G_ITT_SHIFT 8 212 #define B5G_MAXP_MASK 0xff 213 #define B5G_ITT_SHIFT 8 214 #define B5GH_MAXP_MASK 0xff 215 #define B5GL_MAXP_SHIFT 8 216 217 /* All the miriad power offsets */ 218 #define SROM4_2G_CCKPO 156 219 #define SROM4_2G_OFDMPO 157 220 #define SROM4_5G_OFDMPO 159 221 #define SROM4_5GL_OFDMPO 161 222 #define SROM4_5GH_OFDMPO 163 223 #define SROM4_2G_MCSPO 165 224 #define SROM4_5G_MCSPO 173 225 #define SROM4_5GL_MCSPO 181 226 #define SROM4_5GH_MCSPO 189 227 #define SROM4_CDDPO 197 228 #define SROM4_STBCPO 198 229 #define SROM4_BW40PO 199 230 #define SROM4_BWDUPPO 200 231 232 #define SROM4_CRCREV 219 233 234 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 235 * This is acombined srom for both MIMO and SISO boards, usable in 236 * the .130 4Kilobit OTP with hardware redundancy. 237 */ 238 239 #define SROM8_SIGN 64 240 241 #define SROM8_BREV 65 242 243 #define SROM8_BFL0 66 244 #define SROM8_BFL1 67 245 #define SROM8_BFL2 68 246 #define SROM8_BFL3 69 247 248 #define SROM8_MACHI 70 249 #define SROM8_MACMID 71 250 #define SROM8_MACLO 72 251 252 #define SROM8_CCODE 73 253 #define SROM8_REGREV 74 254 255 #define SROM8_LEDBH10 75 256 #define SROM8_LEDBH32 76 257 258 #define SROM8_LEDDC 77 259 260 #define SROM8_AA 78 261 262 #define SROM8_AG10 79 263 #define SROM8_AG32 80 264 265 #define SROM8_TXRXC 81 266 267 #define SROM8_BXARSSI2G 82 268 #define SROM8_BXARSSI5G 83 269 #define SROM8_TRI52G 84 270 #define SROM8_TRI5GHL 85 271 #define SROM8_RXPO52G 86 272 273 #define SROM8_FEM2G 87 274 #define SROM8_FEM5G 88 275 #define SROM8_FEM_ANTSWLUT_MASK 0xf800 276 #define SROM8_FEM_ANTSWLUT_SHIFT 11 277 #define SROM8_FEM_TR_ISO_MASK 0x0700 278 #define SROM8_FEM_TR_ISO_SHIFT 8 279 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8 280 #define SROM8_FEM_PDET_RANGE_SHIFT 3 281 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 282 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1 283 #define SROM8_FEM_TSSIPOS_MASK 0x0001 284 #define SROM8_FEM_TSSIPOS_SHIFT 0 285 286 #define SROM8_THERMAL 89 287 288 /* Temp sense related entries */ 289 #define SROM8_MPWR_RAWTS 90 290 #define SROM8_TS_SLP_OPT_CORRX 91 291 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 292 #define SROM8_FOC_HWIQ_IQSWP 92 293 294 #define SROM8_EXTLNAGAIN 93 295 296 /* Temperature delta for PHY calibration */ 297 #define SROM8_PHYCAL_TEMPDELTA 94 298 299 /* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */ 300 #define SROM8_MPWR_1_AND_2 95 301 302 /* Per-path offsets & fields */ 303 #define SROM8_PATH0 96 304 #define SROM8_PATH1 112 305 #define SROM8_PATH2 128 306 #define SROM8_PATH3 144 307 308 #define SROM8_2G_ITT_MAXP 0 309 #define SROM8_2G_PA 1 310 #define SROM8_5G_ITT_MAXP 4 311 #define SROM8_5GLH_MAXP 5 312 #define SROM8_5G_PA 6 313 #define SROM8_5GL_PA 9 314 #define SROM8_5GH_PA 12 315 316 /* All the miriad power offsets */ 317 #define SROM8_2G_CCKPO 160 318 319 #define SROM8_2G_OFDMPO 161 320 #define SROM8_5G_OFDMPO 163 321 #define SROM8_5GL_OFDMPO 165 322 #define SROM8_5GH_OFDMPO 167 323 324 #define SROM8_2G_MCSPO 169 325 #define SROM8_5G_MCSPO 177 326 #define SROM8_5GL_MCSPO 185 327 #define SROM8_5GH_MCSPO 193 328 329 #define SROM8_CDDPO 201 330 #define SROM8_STBCPO 202 331 #define SROM8_BW40PO 203 332 #define SROM8_BWDUPPO 204 333 334 /* SISO PA parameters are in the path0 spaces */ 335 #define SROM8_SISO 96 336 337 /* Legacy names for SISO PA paramters */ 338 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 339 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 340 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 341 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 342 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 343 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 344 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 345 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 346 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 347 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 348 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 349 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 350 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 351 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 352 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 353 354 #define SROM8_CRCREV 219 355 356 /* SROM REV 9 */ 357 #define SROM9_2GPO_CCKBW20 160 358 #define SROM9_2GPO_CCKBW20UL 161 359 #define SROM9_2GPO_LOFDMBW20 162 360 #define SROM9_2GPO_LOFDMBW20UL 164 361 362 #define SROM9_5GLPO_LOFDMBW20 166 363 #define SROM9_5GLPO_LOFDMBW20UL 168 364 #define SROM9_5GMPO_LOFDMBW20 170 365 #define SROM9_5GMPO_LOFDMBW20UL 172 366 #define SROM9_5GHPO_LOFDMBW20 174 367 #define SROM9_5GHPO_LOFDMBW20UL 176 368 369 #define SROM9_2GPO_MCSBW20 178 370 #define SROM9_2GPO_MCSBW20UL 180 371 #define SROM9_2GPO_MCSBW40 182 372 373 #define SROM9_5GLPO_MCSBW20 184 374 #define SROM9_5GLPO_MCSBW20UL 186 375 #define SROM9_5GLPO_MCSBW40 188 376 #define SROM9_5GMPO_MCSBW20 190 377 #define SROM9_5GMPO_MCSBW20UL 192 378 #define SROM9_5GMPO_MCSBW40 194 379 #define SROM9_5GHPO_MCSBW20 196 380 #define SROM9_5GHPO_MCSBW20UL 198 381 #define SROM9_5GHPO_MCSBW40 200 382 383 #define SROM9_PO_MCS32 202 384 #define SROM9_PO_LOFDM40DUP 203 385 #define SROM9_EU_EDCRSTH 204 386 #define SROM10_EU_EDCRSTH 204 387 #define SROM8_RXGAINERR_2G 205 388 #define SROM8_RXGAINERR_5GL 206 389 #define SROM8_RXGAINERR_5GM 207 390 #define SROM8_RXGAINERR_5GH 208 391 #define SROM8_RXGAINERR_5GU 209 392 #define SROM8_SUBBAND_PPR 210 393 #define SROM8_PCIEINGRESS_WAR 211 394 #define SROM8_EU_EDCRSTH 212 395 #define SROM9_SAR 212 396 397 #define SROM8_NOISELVL_2G 213 398 #define SROM8_NOISELVL_5GL 214 399 #define SROM8_NOISELVL_5GM 215 400 #define SROM8_NOISELVL_5GH 216 401 #define SROM8_NOISELVL_5GU 217 402 #define SROM8_NOISECALOFFSET 218 403 404 #define SROM9_REV_CRC 219 405 406 #define SROM10_CCKPWROFFSET 218 407 #define SROM10_SIGN 219 408 #define SROM10_SWCTRLMAP_2G 220 409 #define SROM10_CRCREV 229 410 411 #define SROM10_WORDS 230 412 #define SROM10_SIGNATURE SROM4_SIGNATURE 413 414 /* SROM REV 11 */ 415 #define SROM11_BREV 65 416 417 #define SROM11_BFL0 66 418 #define SROM11_BFL1 67 419 #define SROM11_BFL2 68 420 #define SROM11_BFL3 69 421 #define SROM11_BFL4 70 422 #define SROM11_BFL5 71 423 424 #define SROM11_MACHI 72 425 #define SROM11_MACMID 73 426 #define SROM11_MACLO 74 427 428 #define SROM11_CCODE 75 429 #define SROM11_REGREV 76 430 431 #define SROM11_LEDBH10 77 432 #define SROM11_LEDBH32 78 433 434 #define SROM11_LEDDC 79 435 436 #define SROM11_AA 80 437 438 #define SROM11_AGBG10 81 439 #define SROM11_AGBG2A0 82 440 #define SROM11_AGA21 83 441 442 #define SROM11_TXRXC 84 443 444 #define SROM11_FEM_CFG1 85 445 #define SROM11_FEM_CFG2 86 446 447 /* Masks and offsets for FEM_CFG */ 448 #define SROM11_FEMCTRL_MASK 0xf800 449 #define SROM11_FEMCTRL_SHIFT 11 450 #define SROM11_PAPDCAP_MASK 0x0400 451 #define SROM11_PAPDCAP_SHIFT 10 452 #define SROM11_TWORANGETSSI_MASK 0x0200 453 #define SROM11_TWORANGETSSI_SHIFT 9 454 #define SROM11_PDGAIN_MASK 0x01f0 455 #define SROM11_PDGAIN_SHIFT 4 456 #define SROM11_EPAGAIN_MASK 0x000e 457 #define SROM11_EPAGAIN_SHIFT 1 458 #define SROM11_TSSIPOSSLOPE_MASK 0x0001 459 #define SROM11_TSSIPOSSLOPE_SHIFT 0 460 #define SROM11_GAINCTRLSPH_MASK 0xf800 461 #define SROM11_GAINCTRLSPH_SHIFT 11 462 463 #define SROM11_THERMAL 87 464 #define SROM11_MPWR_RAWTS 88 465 #define SROM11_TS_SLP_OPT_CORRX 89 466 #define SROM11_XTAL_FREQ 90 467 #define SROM11_5GB0_4080_W0_A1 91 468 #define SROM11_PHYCAL_TEMPDELTA 92 469 #define SROM11_MPWR_1_AND_2 93 470 #define SROM11_5GB0_4080_W1_A1 94 471 #define SROM11_TSSIFLOOR_2G 95 472 #define SROM11_TSSIFLOOR_5GL 96 473 #define SROM11_TSSIFLOOR_5GM 97 474 #define SROM11_TSSIFLOOR_5GH 98 475 #define SROM11_TSSIFLOOR_5GU 99 476 477 /* Masks and offsets for Thermal parameters */ 478 #define SROM11_TEMPS_PERIOD_MASK 0xf0 479 #define SROM11_TEMPS_PERIOD_SHIFT 4 480 #define SROM11_TEMPS_HYSTERESIS_MASK 0x0f 481 #define SROM11_TEMPS_HYSTERESIS_SHIFT 0 482 #define SROM11_TEMPCORRX_MASK 0xfc 483 #define SROM11_TEMPCORRX_SHIFT 2 484 #define SROM11_TEMPSENSE_OPTION_MASK 0x3 485 #define SROM11_TEMPSENSE_OPTION_SHIFT 0 486 487 #define SROM11_PDOFF_2G_40M_A0_MASK 0x000f 488 #define SROM11_PDOFF_2G_40M_A0_SHIFT 0 489 #define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0 490 #define SROM11_PDOFF_2G_40M_A1_SHIFT 4 491 #define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00 492 #define SROM11_PDOFF_2G_40M_A2_SHIFT 8 493 #define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000 494 #define SROM11_PDOFF_2G_40M_VALID_SHIFT 15 495 496 #define SROM11_PDOFF_2G_40M 100 497 #define SROM11_PDOFF_40M_A0 101 498 #define SROM11_PDOFF_40M_A1 102 499 #define SROM11_PDOFF_40M_A2 103 500 #define SROM11_5GB0_4080_W2_A1 103 501 #define SROM11_PDOFF_80M_A0 104 502 #define SROM11_PDOFF_80M_A1 105 503 #define SROM11_PDOFF_80M_A2 106 504 #define SROM11_5GB1_4080_W0_A1 106 505 506 #define SROM11_SUBBAND5GVER 107 507 508 /* Per-path fields and offset */ 509 #define MAX_PATH_SROM_11 3 510 #define SROM11_PATH0 108 511 #define SROM11_PATH1 128 512 #define SROM11_PATH2 148 513 514 #define SROM11_2G_MAXP 0 515 #define SROM11_5GB1_4080_PA 0 516 #define SROM11_2G_PA 1 517 #define SROM11_5GB2_4080_PA 2 518 #define SROM11_RXGAINS1 4 519 #define SROM11_RXGAINS 5 520 #define SROM11_5GB3_4080_PA 5 521 #define SROM11_5GB1B0_MAXP 6 522 #define SROM11_5GB3B2_MAXP 7 523 #define SROM11_5GB0_PA 8 524 #define SROM11_5GB1_PA 11 525 #define SROM11_5GB2_PA 14 526 #define SROM11_5GB3_PA 17 527 528 /* Masks and offsets for rxgains */ 529 #define SROM11_RXGAINS5GTRELNABYPA_MASK 0x8000 530 #define SROM11_RXGAINS5GTRELNABYPA_SHIFT 15 531 #define SROM11_RXGAINS5GTRISOA_MASK 0x7800 532 #define SROM11_RXGAINS5GTRISOA_SHIFT 11 533 #define SROM11_RXGAINS5GELNAGAINA_MASK 0x0700 534 #define SROM11_RXGAINS5GELNAGAINA_SHIFT 8 535 #define SROM11_RXGAINS2GTRELNABYPA_MASK 0x0080 536 #define SROM11_RXGAINS2GTRELNABYPA_SHIFT 7 537 #define SROM11_RXGAINS2GTRISOA_MASK 0x0078 538 #define SROM11_RXGAINS2GTRISOA_SHIFT 3 539 #define SROM11_RXGAINS2GELNAGAINA_MASK 0x0007 540 #define SROM11_RXGAINS2GELNAGAINA_SHIFT 0 541 #define SROM11_RXGAINS5GHTRELNABYPA_MASK 0x8000 542 #define SROM11_RXGAINS5GHTRELNABYPA_SHIFT 15 543 #define SROM11_RXGAINS5GHTRISOA_MASK 0x7800 544 #define SROM11_RXGAINS5GHTRISOA_SHIFT 11 545 #define SROM11_RXGAINS5GHELNAGAINA_MASK 0x0700 546 #define SROM11_RXGAINS5GHELNAGAINA_SHIFT 8 547 #define SROM11_RXGAINS5GMTRELNABYPA_MASK 0x0080 548 #define SROM11_RXGAINS5GMTRELNABYPA_SHIFT 7 549 #define SROM11_RXGAINS5GMTRISOA_MASK 0x0078 550 #define SROM11_RXGAINS5GMTRISOA_SHIFT 3 551 #define SROM11_RXGAINS5GMELNAGAINA_MASK 0x0007 552 #define SROM11_RXGAINS5GMELNAGAINA_SHIFT 0 553 554 /* Power per rate */ 555 #define SROM11_CCKBW202GPO 168 556 #define SROM11_CCKBW20UL2GPO 169 557 #define SROM11_MCSBW202GPO 170 558 #define SROM11_MCSBW202GPO_1 171 559 #define SROM11_MCSBW402GPO 172 560 #define SROM11_MCSBW402GPO_1 173 561 #define SROM11_DOT11AGOFDMHRBW202GPO 174 562 #define SROM11_OFDMLRBW202GPO 175 563 564 #define SROM11_MCSBW205GLPO 176 565 #define SROM11_MCSBW205GLPO_1 177 566 #define SROM11_MCSBW405GLPO 178 567 #define SROM11_MCSBW405GLPO_1 179 568 #define SROM11_MCSBW805GLPO 180 569 #define SROM11_MCSBW805GLPO_1 181 570 #define SROM11_RPCAL_2G 182 571 #define SROM11_RPCAL_5GL 183 572 #define SROM11_MCSBW205GMPO 184 573 #define SROM11_MCSBW205GMPO_1 185 574 #define SROM11_MCSBW405GMPO 186 575 #define SROM11_MCSBW405GMPO_1 187 576 #define SROM11_MCSBW805GMPO 188 577 #define SROM11_MCSBW805GMPO_1 189 578 #define SROM11_RPCAL_5GM 190 579 #define SROM11_RPCAL_5GH 191 580 #define SROM11_MCSBW205GHPO 192 581 #define SROM11_MCSBW205GHPO_1 193 582 #define SROM11_MCSBW405GHPO 194 583 #define SROM11_MCSBW405GHPO_1 195 584 #define SROM11_MCSBW805GHPO 196 585 #define SROM11_MCSBW805GHPO_1 197 586 #define SROM11_RPCAL_5GU 198 587 #define SROM11_PDOFF_2G_CCK 199 588 #define SROM11_MCSLR5GLPO 200 589 #define SROM11_MCSLR5GMPO 201 590 #define SROM11_MCSLR5GHPO 202 591 592 #define SROM11_SB20IN40HRPO 203 593 #define SROM11_SB20IN80AND160HR5GLPO 204 594 #define SROM11_SB40AND80HR5GLPO 205 595 #define SROM11_SB20IN80AND160HR5GMPO 206 596 #define SROM11_SB40AND80HR5GMPO 207 597 #define SROM11_SB20IN80AND160HR5GHPO 208 598 #define SROM11_SB40AND80HR5GHPO 209 599 #define SROM11_SB20IN40LRPO 210 600 #define SROM11_SB20IN80AND160LR5GLPO 211 601 #define SROM11_SB40AND80LR5GLPO 212 602 #define SROM11_TXIDXCAP2G 212 603 #define SROM11_SB20IN80AND160LR5GMPO 213 604 #define SROM11_SB40AND80LR5GMPO 214 605 #define SROM11_TXIDXCAP5G 214 606 #define SROM11_SB20IN80AND160LR5GHPO 215 607 #define SROM11_SB40AND80LR5GHPO 216 608 609 #define SROM11_DOT11AGDUPHRPO 217 610 #define SROM11_DOT11AGDUPLRPO 218 611 612 /* MISC */ 613 #define SROM11_PCIEINGRESS_WAR 220 614 #define SROM11_SAR 221 615 616 #define SROM11_NOISELVL_2G 222 617 #define SROM11_NOISELVL_5GL 223 618 #define SROM11_NOISELVL_5GM 224 619 #define SROM11_NOISELVL_5GH 225 620 #define SROM11_NOISELVL_5GU 226 621 622 #define SROM11_RXGAINERR_2G 227 623 #define SROM11_RXGAINERR_5GL 228 624 #define SROM11_RXGAINERR_5GM 229 625 #define SROM11_RXGAINERR_5GH 230 626 #define SROM11_RXGAINERR_5GU 231 627 628 #define SROM11_EU_EDCRSTH 232 629 #define SROM12_EU_EDCRSTH 232 630 631 #define SROM11_SIGN 64 632 #define SROM11_CRCREV 233 633 634 #define SROM11_WORDS 234 635 #define SROM11_SIGNATURE 0x0634 636 637 /* SROM REV 12 */ 638 #define SROM12_SIGN 64 639 #define SROM12_WORDS 512 640 #define SROM12_SIGNATURE 0x8888 641 #define SROM12_CRCREV 511 642 643 #define SROM12_BFL6 486 644 #define SROM12_BFL7 487 645 646 #define SROM12_MCSBW205GX1PO 234 647 #define SROM12_MCSBW205GX1PO_1 235 648 #define SROM12_MCSBW405GX1PO 236 649 #define SROM12_MCSBW405GX1PO_1 237 650 #define SROM12_MCSBW805GX1PO 238 651 #define SROM12_MCSBW805GX1PO_1 239 652 #define SROM12_MCSLR5GX1PO 240 653 #define SROM12_SB40AND80LR5GX1PO 241 654 #define SROM12_SB20IN80AND160LR5GX1PO 242 655 #define SROM12_SB20IN80AND160HR5GX1PO 243 656 #define SROM12_SB40AND80HR5GX1PO 244 657 658 #define SROM12_MCSBW205GX2PO 245 659 #define SROM12_MCSBW205GX2PO_1 246 660 #define SROM12_MCSBW405GX2PO 247 661 #define SROM12_MCSBW405GX2PO_1 248 662 #define SROM12_MCSBW805GX2PO 249 663 #define SROM12_MCSBW805GX2PO_1 250 664 #define SROM12_MCSLR5GX2PO 251 665 #define SROM12_SB40AND80LR5GX2PO 252 666 #define SROM12_SB20IN80AND160LR5GX2PO 253 667 #define SROM12_SB20IN80AND160HR5GX2PO 254 668 #define SROM12_SB40AND80HR5GX2PO 255 669 670 /* MISC */ 671 #define SROM12_RXGAINS10 483 672 #define SROM12_RXGAINS11 484 673 #define SROM12_RXGAINS12 485 674 675 /* Per-path fields and offset */ 676 #define MAX_PATH_SROM_12 3 677 #define SROM12_PATH0 256 678 #define SROM12_PATH1 328 679 #define SROM12_PATH2 400 680 681 #define SROM12_5GB42G_MAXP 0 682 #define SROM12_2GB0_PA 1 683 #define SROM12_2GB0_PA_W0 1 684 #define SROM12_2GB0_PA_W1 2 685 #define SROM12_2GB0_PA_W2 3 686 #define SROM12_2GB0_PA_W3 4 687 688 #define SROM12_RXGAINS 5 689 #define SROM12_5GB1B0_MAXP 6 690 #define SROM12_5GB3B2_MAXP 7 691 692 #define SROM12_5GB0_PA 8 693 #define SROM12_5GB0_PA_W0 8 694 #define SROM12_5GB0_PA_W1 9 695 #define SROM12_5GB0_PA_W2 10 696 #define SROM12_5GB0_PA_W3 11 697 698 #define SROM12_5GB1_PA 12 699 #define SROM12_5GB1_PA_W0 12 700 #define SROM12_5GB1_PA_W1 13 701 #define SROM12_5GB1_PA_W2 14 702 #define SROM12_5GB1_PA_W3 15 703 704 #define SROM12_5GB2_PA 16 705 #define SROM12_5GB2_PA_W0 16 706 #define SROM12_5GB2_PA_W1 17 707 #define SROM12_5GB2_PA_W2 18 708 #define SROM12_5GB2_PA_W3 19 709 710 #define SROM12_5GB3_PA 20 711 #define SROM12_5GB3_PA_W0 20 712 #define SROM12_5GB3_PA_W1 21 713 #define SROM12_5GB3_PA_W2 22 714 #define SROM12_5GB3_PA_W3 23 715 716 #define SROM12_5GB4_PA 24 717 #define SROM12_5GB4_PA_W0 24 718 #define SROM12_5GB4_PA_W1 25 719 #define SROM12_5GB4_PA_W2 26 720 #define SROM12_5GB4_PA_W3 27 721 722 #define SROM12_2G40B0_PA 28 723 #define SROM12_2G40B0_PA_W0 28 724 #define SROM12_2G40B0_PA_W1 29 725 #define SROM12_2G40B0_PA_W2 30 726 #define SROM12_2G40B0_PA_W3 31 727 728 #define SROM12_5G40B0_PA 32 729 #define SROM12_5G40B0_PA_W0 32 730 #define SROM12_5G40B0_PA_W1 33 731 #define SROM12_5G40B0_PA_W2 34 732 #define SROM12_5G40B0_PA_W3 35 733 734 #define SROM12_5G40B1_PA 36 735 #define SROM12_5G40B1_PA_W0 36 736 #define SROM12_5G40B1_PA_W1 37 737 #define SROM12_5G40B1_PA_W2 38 738 #define SROM12_5G40B1_PA_W3 39 739 740 #define SROM12_5G40B2_PA 40 741 #define SROM12_5G40B2_PA_W0 40 742 #define SROM12_5G40B2_PA_W1 41 743 #define SROM12_5G40B2_PA_W2 42 744 #define SROM12_5G40B2_PA_W3 43 745 746 #define SROM12_5G40B3_PA 44 747 #define SROM12_5G40B3_PA_W0 44 748 #define SROM12_5G40B3_PA_W1 45 749 #define SROM12_5G40B3_PA_W2 46 750 #define SROM12_5G40B3_PA_W3 47 751 752 #define SROM12_5G40B4_PA 48 753 #define SROM12_5G40B4_PA_W0 48 754 #define SROM12_5G40B4_PA_W1 49 755 #define SROM12_5G40B4_PA_W2 50 756 #define SROM12_5G40B4_PA_W3 51 757 758 #define SROM12_5G80B0_PA 52 759 #define SROM12_5G80B0_PA_W0 52 760 #define SROM12_5G80B0_PA_W1 53 761 #define SROM12_5G80B0_PA_W2 54 762 #define SROM12_5G80B0_PA_W3 55 763 764 #define SROM12_5G80B1_PA 56 765 #define SROM12_5G80B1_PA_W0 56 766 #define SROM12_5G80B1_PA_W1 57 767 #define SROM12_5G80B1_PA_W2 58 768 #define SROM12_5G80B1_PA_W3 59 769 770 #define SROM12_5G80B2_PA 60 771 #define SROM12_5G80B2_PA_W0 60 772 #define SROM12_5G80B2_PA_W1 61 773 #define SROM12_5G80B2_PA_W2 62 774 #define SROM12_5G80B2_PA_W3 63 775 776 #define SROM12_5G80B3_PA 64 777 #define SROM12_5G80B3_PA_W0 64 778 #define SROM12_5G80B3_PA_W1 65 779 #define SROM12_5G80B3_PA_W2 66 780 #define SROM12_5G80B3_PA_W3 67 781 782 #define SROM12_5G80B4_PA 68 783 #define SROM12_5G80B4_PA_W0 68 784 #define SROM12_5G80B4_PA_W1 69 785 #define SROM12_5G80B4_PA_W2 70 786 #define SROM12_5G80B4_PA_W3 71 787 788 /* PD offset */ 789 #define SROM12_PDOFF_2G_CCK 472 790 791 #define SROM12_PDOFF_20in40M_5G_B0 473 792 #define SROM12_PDOFF_20in40M_5G_B1 474 793 #define SROM12_PDOFF_20in40M_5G_B2 475 794 #define SROM12_PDOFF_20in40M_5G_B3 476 795 #define SROM12_PDOFF_20in40M_5G_B4 477 796 797 #define SROM12_PDOFF_40in80M_5G_B0 478 798 #define SROM12_PDOFF_40in80M_5G_B1 479 799 #define SROM12_PDOFF_40in80M_5G_B2 480 800 #define SROM12_PDOFF_40in80M_5G_B3 481 801 #define SROM12_PDOFF_40in80M_5G_B4 482 802 803 #define SROM12_PDOFF_20in80M_5G_B0 488 804 #define SROM12_PDOFF_20in80M_5G_B1 489 805 #define SROM12_PDOFF_20in80M_5G_B2 490 806 #define SROM12_PDOFF_20in80M_5G_B3 491 807 #define SROM12_PDOFF_20in80M_5G_B4 492 808 809 #define SROM12_GPDN_L 91 /* GPIO pull down bits [15:0] */ 810 #define SROM12_GPDN_H 233 /* GPIO pull down bits [31:16] */ 811 812 #define SROM13_SIGN 64 813 #define SROM13_WORDS 590 814 #define SROM13_SIGNATURE 0x4d55 815 #define SROM13_CRCREV 589 816 817 /* Per-path fields and offset */ 818 #define MAX_PATH_SROM_13 4 819 #define SROM13_PATH0 256 820 #define SROM13_PATH1 328 821 #define SROM13_PATH2 400 822 #define SROM13_PATH3 512 823 #define SROM13_RXGAINS 5 824 825 #define SROM13_XTALFREQ 90 826 827 #define SROM13_PDOFFSET20IN40M2G 94 828 #define SROM13_PDOFFSET20IN40M2GCORE3 95 829 #define SROM13_SB20IN40HRLRPOX 96 830 831 #define SROM13_RXGAINS1CORE3 97 832 833 #define SROM13_PDOFFSET20IN40M5GCORE3 98 834 #define SROM13_PDOFFSET20IN40M5GCORE3_1 99 835 836 #define SROM13_ANTGAIN_BANDBGA 100 837 838 #define SROM13_PDOFFSET40IN80M5GCORE3 105 839 #define SROM13_PDOFFSET40IN80M5GCORE3_1 106 840 841 /* power per rate */ 842 #define SROM13_MCS1024QAM2GPO 108 843 #define SROM13_MCS1024QAM5GLPO 109 844 #define SROM13_MCS1024QAM5GLPO_1 110 845 #define SROM13_MCS1024QAM5GMPO 111 846 #define SROM13_MCS1024QAM5GMPO_1 112 847 #define SROM13_MCS1024QAM5GHPO 113 848 #define SROM13_MCS1024QAM5GHPO_1 114 849 #define SROM13_MCS1024QAM5GX1PO 115 850 #define SROM13_MCS1024QAM5GX1PO_1 116 851 #define SROM13_MCS1024QAM5GX2PO 117 852 #define SROM13_MCS1024QAM5GX2PO_1 118 853 854 #define SROM13_MCSBW1605GLPO 119 855 #define SROM13_MCSBW1605GLPO_1 120 856 #define SROM13_MCSBW1605GMPO 121 857 #define SROM13_MCSBW1605GMPO_1 122 858 #define SROM13_MCSBW1605GHPO 123 859 #define SROM13_MCSBW1605GHPO_1 124 860 861 #define SROM13_MCSBW1605GX1PO 125 862 #define SROM13_MCSBW1605GX1PO_1 126 863 #define SROM13_MCSBW1605GX2PO 127 864 #define SROM13_MCSBW1605GX2PO_1 128 865 866 #define SROM13_ULBPPROFFS5GB0 129 867 #define SROM13_ULBPPROFFS5GB1 130 868 #define SROM13_ULBPPROFFS5GB2 131 869 #define SROM13_ULBPPROFFS5GB3 132 870 #define SROM13_ULBPPROFFS5GB4 133 871 #define SROM13_ULBPPROFFS2G 134 872 873 #define SROM13_MCS8POEXP 135 874 #define SROM13_MCS8POEXP_1 136 875 #define SROM13_MCS9POEXP 137 876 #define SROM13_MCS9POEXP_1 138 877 #define SROM13_MCS10POEXP 139 878 #define SROM13_MCS10POEXP_1 140 879 #define SROM13_MCS11POEXP 141 880 #define SROM13_MCS11POEXP_1 142 881 #define SROM13_ULBPDOFFS5GB0A0 143 882 #define SROM13_ULBPDOFFS5GB0A1 144 883 #define SROM13_ULBPDOFFS5GB0A2 145 884 #define SROM13_ULBPDOFFS5GB0A3 146 885 #define SROM13_ULBPDOFFS5GB1A0 147 886 #define SROM13_ULBPDOFFS5GB1A1 148 887 #define SROM13_ULBPDOFFS5GB1A2 149 888 #define SROM13_ULBPDOFFS5GB1A3 150 889 #define SROM13_ULBPDOFFS5GB2A0 151 890 #define SROM13_ULBPDOFFS5GB2A1 152 891 #define SROM13_ULBPDOFFS5GB2A2 153 892 #define SROM13_ULBPDOFFS5GB2A3 154 893 #define SROM13_ULBPDOFFS5GB3A0 155 894 #define SROM13_ULBPDOFFS5GB3A1 156 895 #define SROM13_ULBPDOFFS5GB3A2 157 896 #define SROM13_ULBPDOFFS5GB3A3 158 897 #define SROM13_ULBPDOFFS5GB4A0 159 898 #define SROM13_ULBPDOFFS5GB4A1 160 899 #define SROM13_ULBPDOFFS5GB4A2 161 900 #define SROM13_ULBPDOFFS5GB4A3 162 901 #define SROM13_ULBPDOFFS2GA0 163 902 #define SROM13_ULBPDOFFS2GA1 164 903 #define SROM13_ULBPDOFFS2GA2 165 904 #define SROM13_ULBPDOFFS2GA3 166 905 906 #define SROM13_RPCAL5GB4 199 907 #define SROM13_RPCAL2GCORE3 101 908 #define SROM13_RPCAL5GB01CORE3 102 909 #define SROM13_RPCAL5GB23CORE3 103 910 911 #define SROM13_SW_TXRX_MASK 104 912 913 #define SROM13_EU_EDCRSTH 232 914 915 #define SROM13_SWCTRLMAP4_CFG 493 916 #define SROM13_SWCTRLMAP4_TX2G_FEM3TO0 494 917 #define SROM13_SWCTRLMAP4_RX2G_FEM3TO0 495 918 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0 496 919 #define SROM13_SWCTRLMAP4_MISC2G_FEM3TO0 497 920 #define SROM13_SWCTRLMAP4_TX5G_FEM3TO0 498 921 #define SROM13_SWCTRLMAP4_RX5G_FEM3TO0 499 922 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0 500 923 #define SROM13_SWCTRLMAP4_MISC5G_FEM3TO0 501 924 #define SROM13_SWCTRLMAP4_TX2G_FEM7TO4 502 925 #define SROM13_SWCTRLMAP4_RX2G_FEM7TO4 503 926 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4 504 927 #define SROM13_SWCTRLMAP4_MISC2G_FEM7TO4 505 928 #define SROM13_SWCTRLMAP4_TX5G_FEM7TO4 506 929 #define SROM13_SWCTRLMAP4_RX5G_FEM7TO4 507 930 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4 508 931 #define SROM13_SWCTRLMAP4_MISC5G_FEM7TO4 509 932 933 #define SROM13_PDOFFSET20IN80M5GCORE3 510 934 #define SROM13_PDOFFSET20IN80M5GCORE3_1 511 935 936 #define SROM13_NOISELVLCORE3 584 937 #define SROM13_NOISELVLCORE3_1 585 938 #define SROM13_RXGAINERRCORE3 586 939 #define SROM13_RXGAINERRCORE3_1 587 940 941 #define SROM13_PDOFF_2G_CCK_20M 167 942 943 #define SROM15_CALDATA_WORDS 943 944 #define SROM15_CAL_OFFSET_LOC 68 945 #define MAX_IOCTL_TXCHUNK_SIZE 1500 946 #define SROM15_MAX_CAL_SIZE 1886 947 #define SROM15_SIGNATURE 0x110c 948 #define SROM15_WORDS 1024 949 #define SROM15_MACHI 65 950 #define SROM15_CRCREV 1023 951 #define SROM15_BRDREV 69 952 #define SROM15_CCODE 70 953 #define SROM15_REGREV 71 954 #define SROM15_SIGN 64 955 956 #define SROM16_SIGN 128 957 #define SROM16_WORDS 1024 958 #define SROM16_SIGNATURE 0x4357 959 #define SROM16_CRCREV 1023 960 #define SROM16_MACHI 129 961 #define SROM16_CALDATA_OFFSET_LOC 132 962 #define SROM16_BOARDREV 133 963 #define SROM16_CCODE 134 964 #define SROM16_REGREV 135 965 966 #define SROM_CALDATA_WORDS 832 967 968 #define SROM17_SIGN 64 969 #define SROM17_BRDREV 65 970 #define SROM17_MACADDR 66 971 #define SROM17_CCODE 69 972 #define SROM17_CALDATA 70 973 #define SROM17_GCALTMP 71 974 975 #define SROM17_C0SRD202G 72 976 #define SROM17_C0SRD202G_1 73 977 #define SROM17_C0SRD205GL 74 978 #define SROM17_C0SRD205GL_1 75 979 #define SROM17_C0SRD205GML 76 980 #define SROM17_C0SRD205GML_1 77 981 #define SROM17_C0SRD205GMU 78 982 #define SROM17_C0SRD205GMU_1 79 983 #define SROM17_C0SRD205GH 80 984 #define SROM17_C0SRD205GH_1 81 985 986 #define SROM17_C1SRD202G 82 987 #define SROM17_C1SRD202G_1 83 988 #define SROM17_C1SRD205GL 84 989 #define SROM17_C1SRD205GL_1 85 990 #define SROM17_C1SRD205GML 86 991 #define SROM17_C1SRD205GML_1 87 992 #define SROM17_C1SRD205GMU 88 993 #define SROM17_C1SRD205GMU_1 89 994 #define SROM17_C1SRD205GH 90 995 #define SROM17_C1SRD205GH_1 91 996 997 #define SROM17_TRAMMAGIC 92 998 #define SROM17_TRAMMAGIC_1 93 999 #define SROM17_TRAMDATA 94 1000 1001 #define SROM17_WORDS 256 1002 #define SROM17_CRCREV 255 1003 #define SROM17_CALDATA_WORDS 161 1004 #define SROM17_SIGNATURE 0x1103 /* 4355 in hex format */ 1005 1006 typedef struct { 1007 uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 1008 uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 1009 uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 1010 uint8 triso; /* TR switch isolation */ 1011 uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 1012 } srom_fem_t; 1013 1014 #endif /* _bcmsrom_fmt_h_ */ 1015