1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: Chip core irq >= 0 define. 15 * 16 * Create: 2021-06-16 17 */ 18 19 #ifndef CHIP_CORE_IRQ_H 20 #define CHIP_CORE_IRQ_H 21 22 #define LOCAL_INTERRUPT0 26 23 typedef enum core_irq { 24 /* ------------------- Processor Interrupt Numbers ------------------------------ */ 25 TIMER_0_IRQN = LOCAL_INTERRUPT0 + 0, 26 TIMER_1_IRQN = LOCAL_INTERRUPT0 + 1, 27 TIMER_2_IRQN = LOCAL_INTERRUPT0 + 2, 28 RTC_0_IRQN = LOCAL_INTERRUPT0 + 3, 29 RESERVED0_IRQN = LOCAL_INTERRUPT0 + 4, 30 I2C_0_IRQN = LOCAL_INTERRUPT0 + 5, 31 I2C_1_IRQN = LOCAL_INTERRUPT0 + 6, 32 GPIO_0_IRQN = LOCAL_INTERRUPT0 + 7, 33 GPIO_1_IRQN = LOCAL_INTERRUPT0 + 8, 34 GPIO_2_IRQN = LOCAL_INTERRUPT0 + 9, 35 SOFT_INT0_IRQN = LOCAL_INTERRUPT0 + 10, 36 SOFT_INT1_IRQN = LOCAL_INTERRUPT0 + 11, 37 SOFT_INT2_IRQN = LOCAL_INTERRUPT0 + 12, 38 SOFT_INT3_IRQN = LOCAL_INTERRUPT0 + 13, 39 COEX_WL_IRQN = LOCAL_INTERRUPT0 + 14, 40 COEX_BT_INT = LOCAL_INTERRUPT0 + 15, 41 COEX_WIFI_RESUME_IRQN = LOCAL_INTERRUPT0 + 16, 42 QSPI0_2CS_IRQN = LOCAL_INTERRUPT0 + 17, 43 WLPHY_IRQN = LOCAL_INTERRUPT0 + 18, 44 WLMAC_IRQN = LOCAL_INTERRUPT0 + 19, 45 BT_BB_BLE_IRQN = LOCAL_INTERRUPT0 + 20, 46 BT_BB_GLE_IRQN = LOCAL_INTERRUPT0 + 21, 47 TSENSOR_IRQN = LOCAL_INTERRUPT0 + 22, 48 PMU_CMU_ERR_IRQN = LOCAL_INTERRUPT0 + 23, 49 DIAG_IRQN = LOCAL_INTERRUPT0 + 24, 50 I2S_IRQN = LOCAL_INTERRUPT0 + 25, 51 QSPI_IRQN = LOCAL_INTERRUPT0 + 26, 52 UART_0_IRQN = LOCAL_INTERRUPT0 + 27, 53 UART_1_IRQN = LOCAL_INTERRUPT0 + 28, 54 UART_2_IRQN = LOCAL_INTERRUPT0 + 29, 55 PWM_ABNOR_IRQN = LOCAL_INTERRUPT0 + 30, 56 PWM_CFG_IRQN = LOCAL_INTERRUPT0 + 31, 57 SFC_IRQN = LOCAL_INTERRUPT0 + 32, 58 DMA_IRQN = LOCAL_INTERRUPT0 + 33, 59 TIMER_ABNOR_IRQN = LOCAL_INTERRUPT0 + 34, 60 I2S_TX_IRQN = LOCAL_INTERRUPT0 + 35, 61 I2S_RX_IRQN = LOCAL_INTERRUPT0 + 36, 62 PKE_REE_IRQN = LOCAL_INTERRUPT0 + 37, 63 SPACC_REE_IRQN = LOCAL_INTERRUPT0 + 38, 64 RKP_REE_IRQN = LOCAL_INTERRUPT0 + 39, 65 KLAD_REE_IRQN = LOCAL_INTERRUPT0 + 40, 66 SLP_UART_RX_WAKE_IRQN = LOCAL_INTERRUPT0 + 41, 67 TIMING_GEN_INT = LOCAL_INTERRUPT0 + 42, 68 MAC_MONITOR_IRQN = LOCAL_INTERRUPT0 + 43, 69 MEM_MONITOR_IRQN = LOCAL_INTERRUPT0 + 44, 70 TCM_MONITOR_IRQN = LOCAL_INTERRUPT0 + 45, 71 LSADC_IRQNR = LOCAL_INTERRUPT0 + 46, 72 BUTT_IRQN 73 } core_irq_t; 74 75 #endif 76