1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file ck_usart.h 18 * @brief header file for usart driver 19 * @version V1.0 20 * @date 02. June 2017 21 ******************************************************************************/ 22 #ifndef __CK_USART_H 23 #define __CK_USART_H 24 25 #include <stdio.h> 26 #include "errno.h" 27 #include "soc.h" 28 29 #define BAUDRATE_DEFAULT 19200 30 #define UART_BUSY_TIMEOUT 1000000 31 #define UART_RECEIVE_TIMEOUT 1000 32 #define UART_TRANSMIT_TIMEOUT 1000 33 #define UART_MAX_FIFO 0x10 34 /* UART register bit definitions */ 35 36 #define USR_UART_BUSY 0x01 37 #define USR_UART_TFE 0x04 38 #define USR_UART_RFNE 0x08 39 #define LSR_DATA_READY 0x01 40 #define LSR_THR_EMPTY 0x20 41 #define IER_RDA_INT_ENABLE 0x01 42 #define IER_THRE_INT_ENABLE 0x02 43 #define IIR_RECV_LINE_ENABLE 0x04 44 #define IIR_NO_ISQ_PEND 0x01 45 46 #define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */ 47 #define LCR_PARITY_ENABLE 0x08 /* parity enabled */ 48 #define LCR_PARITY_EVEN 0x10 /* Even parity enabled */ 49 #define LCR_PARITY_ODD 0xef /* Odd parity enabled */ 50 #define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */ 51 #define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */ 52 #define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */ 53 #define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */ 54 #define LCR_STOP_BIT1 0xfb /* 1 stop bit */ 55 #define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */ 56 57 #define DW_LSR_PFE 0x80 58 #define DW_LSR_TEMT 0x40 59 #define DW_LSR_THRE 0x40 60 #define DW_LSR_BI 0x10 61 #define DW_LSR_FE 0x08 62 #define DW_LSR_PE 0x04 63 #define DW_LSR_OE 0x02 64 #define DW_LSR_DR 0x01 65 #define DW_LSR_TRANS_EMPTY 0x20 66 67 #define DW_IIR_THR_EMPTY 0x02 /* threshold empty */ 68 #define DW_IIR_RECV_DATA 0x04 /* received data available */ 69 #define DW_IIR_RECV_LINE 0x06 /* receiver line status */ 70 #define DW_IIR_CHAR_TIMEOUT 0x0c /* character timeout */ 71 72 typedef struct { 73 union { 74 __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */ 75 __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */ 76 __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */ 77 }; 78 union { 79 __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */ 80 __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ 81 }; 82 __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */ 83 __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */ 84 uint32_t RESERVED0; 85 __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */ 86 __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */ 87 uint32_t RESERVED1[24]; 88 __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */ 89 } ck_usart_reg_t; 90 91 #endif /* __CK_USART_H */ 92