1 /*
2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /******************************************************************************
18 * @file core_802.h
19 * @brief CSI 802 Core Peripheral Access Layer Header File
20 * @version V1.0
21 * @date 02. June 2017
22 ******************************************************************************/
23
24 #ifndef __CORE_802_H_GENERIC
25 #define __CORE_802_H_GENERIC
26
27 #include <stdint.h>
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /*******************************************************************************
34 * CSI definitions
35 ******************************************************************************/
36 /**
37 \ingroup Ck802
38 @{
39 */
40
41 /* CSI CK802 definitions */
42 #define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
43 #define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
44 #define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \
45 __CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */
46 #ifndef __CK80X
47 #define __CK80X (0x02U) /*!< CK80X Core */
48 #endif
49
50 /** __FPU_USED indicates whether an FPU is used or not.
51 This core does not support an FPU at all
52 */
53 #define __FPU_USED 0U
54
55 #if defined ( __GNUC__ )
56 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
57 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
58 #endif
59 #endif
60
61 #ifdef __cplusplus
62 }
63 #endif
64
65 #endif /* __CORE_CK802_H_GENERIC */
66
67 #ifndef __CSI_GENERIC
68
69 #ifndef __CORE_CK802_H_DEPENDANT
70 #define __CORE_CK802_H_DEPENDANT
71
72 #ifdef __cplusplus
73 extern "C" {
74 #endif
75
76 /* check device defines and use defaults */
77 #ifndef __CK802_REV
78 #define __CK802_REV 0x0000U
79 #endif
80
81 #ifndef __VIC_PRIO_BITS
82 #define __VIC_PRIO_BITS 2U
83 #endif
84
85 #ifndef __Vendor_SysTickConfig
86 #define __Vendor_SysTickConfig 1U
87 #endif
88
89 #ifndef __GSR_GCR_PRESENT
90 #define __GSR_GCR_PRESENT 0U
91 #endif
92
93 #ifndef __MPU_PRESENT
94 #define __MPU_PRESENT 1U
95 #endif
96
97 #ifndef __ICACHE_PRESENT
98 #define __ICACHE_PRESENT 1U
99 #endif
100
101 #ifndef __DCACHE_PRESENT
102 #define __DCACHE_PRESENT 1U
103 #endif
104
105 #include <csi_gcc.h>
106
107 /* IO definitions (access restrictions to peripheral registers) */
108 /**
109 \defgroup CSI_glob_defs CSI Global Defines
110
111 <strong>IO Type Qualifiers</strong> are used
112 \li to specify the access to peripheral variables.
113 \li for automatic generation of peripheral register debug information.
114 */
115 #ifdef __cplusplus
116 #define __I volatile /*!< Defines 'read only' permissions */
117 #else
118 #define __I volatile const /*!< Defines 'read only' permissions */
119 #endif
120 #define __O volatile /*!< Defines 'write only' permissions */
121 #define __IO volatile /*!< Defines 'read / write' permissions */
122
123 /* following defines should be used for structure members */
124 #define __IM volatile const /*! Defines 'read only' structure member permissions */
125 #define __OM volatile /*! Defines 'write only' structure member permissions */
126 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
127
128 /*@} end of group CK802 */
129
130 /*******************************************************************************
131 * Register Abstraction
132 Core Register contain:
133 - Core Register
134 - Core VIC Register
135 - Core Cache Register
136 - Core CoreTIM Register
137 ******************************************************************************/
138 /**
139 \defgroup CSI_core_register Defines and Type Definitions
140 \brief Type definitions and defines for CK80X processor based devices.
141 */
142
143 /**
144 \ingroup CSI_core_register
145 \defgroup CSI_CORE Status and Control Registers
146 \brief Core Register type definitions.
147 @{
148 */
149
150 /**
151 \brief Access Processor Status Register(PSR)struct definition.
152 */
153 typedef union {
154 struct {
155 uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
156 uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
157 uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
158 uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
159 uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
160 uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
161 uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
162 uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
163 uint32_t _reserved2: 3; /*!< bit: 24..26 Reserved */
164 uint32_t SC: 1; /*!< bit: 27 Secure call bit */
165 uint32_t HS: 1; /*!< bit: 28 Hardware stacked bit */
166 uint32_t SP: 1; /*!< bit: 29 Secure pending bit */
167 uint32_t T: 1; /*!< bit: 30 TEE mode bit */
168 uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
169 } b; /*!< Structure Access by bit */
170 uint32_t w; /*!< Type Access by whole register */
171 } PSR_Type;
172
173 /* PSR Register Definitions */
174 #define PSR_S_Pos 31U /*!< PSR: S Position */
175 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
176
177 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
178 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
179
180 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
181 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
182
183 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
184 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
185
186 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
187 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
188
189 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
190 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
191
192 #define PSR_C_Pos 0U /*!< PSR: C Position */
193 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
194
195 /**
196 \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
197 */
198 typedef union {
199 struct {
200 uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
201 uint32_t _reserved0: 5; /*!< bit: 2.. 6 Reserved */
202 uint32_t BE: 1; /*!< bit: 7 Endian mode */
203 uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
204 uint32_t _reserved1: 2; /*!< bit: 11..12 Reserved */
205 uint32_t BE_V2: 1; /*!< bit: 13 V2 Endian mode */
206 uint32_t _reserved2: 18; /*!< bit: 14..31 Reserved */
207 } b; /*!< Structure Access by bit */
208 uint32_t w; /*!< Type Access by whole register */
209 } CCR_Type;
210
211 /* CCR Register Definitions */
212 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
213 #define CCR_BE_V2_Msk (0x1UL << CCR_BE_V2_Pos) /*!< CCR: BE_V2 Mask */
214
215 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
216 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
217
218 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
219 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
220
221 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
222 #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
223
224 /**
225 \brief Consortium definition for accessing high ease access permission configuration registers(CAPR, CR<19,0>)
226 */
227 typedef union {
228 struct {
229 uint32_t X0: 1; /*!< bit: 0 Non executable attribute setting */
230 uint32_t X1: 1; /*!< bit: 1 Non executable attribute setting */
231 uint32_t X2: 1; /*!< bit: 2 Non executable attribute setting */
232 uint32_t X3: 1; /*!< bit: 3 Non executable attribute setting */
233 uint32_t X4: 1; /*!< bit: 4 Non executable attribute setting */
234 uint32_t X5: 1; /*!< bit: 5 Non executable attribute setting */
235 uint32_t X6: 1; /*!< bit: 6 Non executable attribute setting */
236 uint32_t X7: 1; /*!< bit: 7 Non executable attribute setting */
237 uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
238 uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
239 uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
240 uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
241 uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
242 uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
243 uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
244 uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
245 uint32_t S0: 1; /*!< bit: 24 Security property settings */
246 uint32_t S1: 1; /*!< bit: 25 Security property settings */
247 uint32_t S2: 1; /*!< bit: 26 Security property settings */
248 uint32_t S3: 1; /*!< bit: 27 Security property settings */
249 uint32_t S4: 1; /*!< bit: 28 Security property settings */
250 uint32_t S5: 1; /*!< bit: 29 Security property settings */
251 uint32_t S6: 1; /*!< bit: 30 Security property settings */
252 uint32_t S7: 1; /*!< bit: 31 Security property settings */
253 } b; /*!< Structure Access by bit */
254 uint32_t w; /*!< Type Access by whole register */
255 } CAPR_Type;
256
257 /* CAPR Register Definitions */
258 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
259 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
260
261 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
262 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
263
264 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
265 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
266
267 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
268 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
269
270 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
271 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
272
273 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
274 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
275
276 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
277 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
278
279 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
280 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
281
282 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
283 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
284
285 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
286 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
287
288 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
289 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
290
291 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
292 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
293
294 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
295 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
296
297 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
298 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
299
300 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
301 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
302
303 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
304 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
305
306 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
307 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
308
309 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
310 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
311
312 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
313 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
314
315 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
316 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
317
318 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
319 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
320
321 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
322 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
323
324 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
325 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
326
327 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
328 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
329
330 /**
331 \brief Consortium definition for accessing control register(PACR, CR<20,0>).
332 */
333 typedef union {
334 struct {
335 uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
336 uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
337 uint32_t _reserved0: 1; /*!< bit: 6 Reserved */
338 uint32_t base_addr: 25; /*!< bit: 7..31 The high position of the address of a protected area */
339 } b; /*!< Structure Access by bit */
340 uint32_t w; /*!< Type Access by whole register */
341 } PACR_Type;
342
343 /* PACR Register Definitions */
344 #define PACR_BASE_ADDR_Pos 7U /*!< PACR: base_addr Position */
345 #define PACR_BASE_ADDR_Msk (0x1FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
346
347 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
348 #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
349
350 #define PACR_E_Pos 0U /*!< PACR: E Position */
351 #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
352
353 /**
354 \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
355 */
356 typedef union {
357 struct {
358 uint32_t RID: 3; /*!< bit: 0.. 2 Protected area index value */
359 uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
360 } b; /*!< Structure Access by bit */
361 uint32_t w; /*!< Type Access by whole register */
362 } PRSR_Type;
363
364 /* PRSR Register Definitions */
365 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
366 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
367
368 /**
369 \brief Consortium definition for CPU Hint Register(CHR, CR<31,0>).
370 */
371 typedef union {
372 struct {
373 uint32_t _reserved0: 4; /*!< bit: 0.. 3 Reserved */
374 uint32_t IAE: 1; /*!< bit: 4 Interrupt response acceleration enable */
375 uint32_t _reserved1: 9; /*!< bit: 5..13 Reserved */
376 uint32_t ISE: 1; /*!< bit: 14 Interrupt SP enable */
377 uint32_t HS_EXP: 1; /*!< bit: 15 Exception bit for TEE world switch */
378 uint32_t SRST_VAL: 16; /*!< bit: 16..31 Software reset decision value */
379 } b;
380 uint32_t w;
381 } CHR_Type;
382
383 /* CHR Register Definitions */
384 #define CHR_IAE_Pos 4U /*!< CHR: IAE Position */
385 #define CHR_IAE_Msk (0x1UL << CHR_IAE_Pos) /*!< CHR: IAE Mask */
386 #define CHR_ISE_Pos 14U /*!< CHR: ISE Position */
387 #define CHR_ISE_Msk (0x1UL << CHR_ISE_Pos) /*!< CHR: ISE Mask */
388 #define CHR_HS_EXP_Pos 15U /*!< CHR: HS_EXP Position */
389 #define CHR_HS_EXP_Msk (0x1UL << CHR_HS_EXP_Pos) /*!< CHR: HS_EXP Mask */
390 #define CHR_SRST_VAL_Pos 16U /*!< CHR: SRST_VAL Position */
391 #define CHR_SRST_VAL_Mask (0xFFFFUL << CHR_SRST_VAL_Pos) /*!< CHR: SRST_VAL Mask */
392
393 /*@} end of group CSI_CORE */
394
395
396 /**
397 \ingroup CSI_core_register
398 \defgroup CSI_VIC Vectored Interrupt Controller (VIC)
399 \brief Type definitions for the VIC Registers
400 @{
401 */
402
403 /**
404 \brief Access to the structure of a vector interrupt controller.
405 */
406 typedef struct {
407 __IOM uint32_t ISER[4U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
408 uint32_t RESERVED0[12U];
409 __IOM uint32_t IWER[4U]; /*!< Offset: 0x040 (R/W) Interrupt wake-up set register */
410 uint32_t RESERVED1[12U];
411 __IOM uint32_t ICER[4U]; /*!< Offset: 0x080 (R/W) Interrupt clear enable register */
412 uint32_t RESERVED2[12U];
413 __IOM uint32_t IWDR[4U]; /*!< Offset: 0x0c0 (R/W) Interrupt wake-up clear register */
414 uint32_t RESERVED3[12U];
415 __IOM uint32_t ISPR[4U]; /*!< Offset: 0x100 (R/W) Interrupt set pend register */
416 uint32_t RESERVED4[12U];
417 __IOM uint32_t ISSR[4U]; /*!< Offset: 0x140 (R/W) Security interrupt set register */
418 uint32_t RESERVED5[12U];
419 __IOM uint32_t ICPR[4U]; /*!< Offset: 0x180 (R/W) Interrupt clear pend register */
420 uint32_t RESERVED6[12U];
421 __IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register */
422 uint32_t RESERVED7[12U];
423 __IOM uint32_t IABR[4U]; /*!< Offset: 0x200 (R/W) Interrupt answer stateregister */
424 uint32_t RESERVED8[60U];
425 __IOM uint32_t IPR[32U]; /*!< Offset: 0x300 (R/W) Interrupt priority register */
426 uint32_t RESERVED9[480U];
427 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) Interrupt state register */
428 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) Interrupt priority thershold register */
429 __IOM uint32_t TSPEND; /*!< Offset: 0xB08 (R/W) Task pending register */
430 __IOM uint32_t TSABR; /*!< Offset: 0xB0c (R/W) Tspend acknowledge register */
431 __IOM uint32_t TSPR; /*!< Offset: 0xB10 (R/W) Tspend priority register */
432 } VIC_Type;
433
434 /*@} end of group CSI_VIC */
435
436 /**
437 \ingroup CSI_core_register
438 \defgroup CSI_CACHE
439 \brief Type definitions for the cache Registers
440 @{
441 */
442
443 /**
444 \brief On chip cache structure.
445 */
446 typedef struct
447 {
448 __IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
449 __IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
450 __IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
451 uint32_t RSERVED0[1015U];
452 __IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analysis control register */
453 __IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
454 __IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
455 } CACHE_Type;
456
457 /* CACHE Register Definitions */
458 #define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
459 #define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
460
461 #define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
462 #define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
463
464 #define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
465 #define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
466
467 #define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
468 #define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
469
470 #define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
471 #define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
472
473 #define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
474 #define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
475
476 #define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
477 #define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
478
479 #define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
480 #define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
481
482 #define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
483 #define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
484
485 #define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
486 #define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
487
488 #define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
489 #define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
490
491 #define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
492 #define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
493
494 #define CACHE_CRCR_4K 0xB /* 01011 */
495 #define CACHE_CRCR_8K 0xC /* 01100 */
496 #define CACHE_CRCR_16K 0xD /* 01101 */
497 #define CACHE_CRCR_32K 0xE /* 01110 */
498 #define CACHE_CRCR_64K 0xF /* 01111 */
499 #define CACHE_CRCR_128K 0x10 /* 10000 */
500 #define CACHE_CRCR_256K 0x11 /* 10001 */
501 #define CACHE_CRCR_512K 0x12 /* 10010 */
502 #define CACHE_CRCR_1M 0x13 /* 10011 */
503 #define CACHE_CRCR_2M 0x14 /* 10100 */
504 #define CACHE_CRCR_4M 0x15 /* 10101 */
505 #define CACHE_CRCR_8M 0x16 /* 10110 */
506 #define CACHE_CRCR_16M 0x17 /* 10111 */
507 #define CACHE_CRCR_32M 0x18 /* 11000 */
508 #define CACHE_CRCR_64M 0x19 /* 11001 */
509 #define CACHE_CRCR_128M 0x1A /* 11010 */
510 #define CACHE_CRCR_256M 0x1B /* 11011 */
511 #define CACHE_CRCR_512M 0x1C /* 11100 */
512 #define CACHE_CRCR_1G 0x1D /* 11101 */
513 #define CACHE_CRCR_2G 0x1E /* 11110 */
514 #define CACHE_CRCR_4G 0x1F /* 11111 */
515
516 /*@} end of group CSI_CACHE */
517
518
519 /**
520 \ingroup CSI_core_register
521 \defgroup CSI_SysTick System Tick Timer (CORET)
522 \brief Type definitions for the System Timer Registers.
523 @{
524 */
525
526 /**
527 \brief The data structure of the access system timer.
528 */
529 typedef struct {
530 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
531 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
532 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
533 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
534 } CORET_Type;
535
536 /* CORET Control / Status Register Definitions */
537 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
538 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
539
540 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
541 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
542
543 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
544 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
545
546 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
547 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
548
549 /* CORET Reload Register Definitions */
550 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
551 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
552
553 /* CORET Current Register Definitions */
554 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
555 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
556
557 /* CORET Calibration Register Definitions */
558 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
559 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
560
561 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
562 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
563
564 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
565 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
566
567 /*@} end of group CSI_SysTick */
568
569 /**
570 \ingroup CSI_core_register
571 \defgroup CSI_DCC
572 \brief Type definitions for the DCC.
573 @{
574 */
575
576 /**
577 \brief Access to the data structure of DCC.
578 */
579 typedef struct {
580 uint32_t RESERVED0[13U];
581 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
582 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
583 uint32_t RESERVED1[6U];
584 union {
585 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
586 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
587 };
588
589 } DCC_Type;
590
591 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
592 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
593
594 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
595 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
596
597 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
598 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
599
600 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
601 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
602
603 /*@} end of group CSI_DCC */
604
605
606 /**
607 \ingroup CSI_core_register
608 \defgroup CSI_core_bitfield Core register bit field macros
609 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
610 @{
611 */
612
613 /**
614 \brief Mask and shift a bit field value for use in a register bit range.
615 \param[in] field Name of the register bit field.
616 \param[in] value Value of the bit field.
617 \return Masked and shifted value.
618 */
619 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
620
621 /**
622 \brief Mask and shift a register value to extract a bit filed value.
623 \param[in] field Name of the register bit field.
624 \param[in] value Value of register.
625 \return Masked and shifted bit field value.
626 */
627 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
628
629 /*@} end of group CSI_core_bitfield */
630
631 /**
632 \ingroup CSI_core_register
633 \defgroup CSI_core_base Core Definitions
634 \brief Definitions for base addresses, unions, and structures.
635 @{
636 */
637
638 /* Memory mapping of CK802 Hardware */
639 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
640 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
641 #define VIC_BASE (TCIP_BASE + 0x0100UL) /*!< VIC Base Address */
642 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
643 #define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
644
645 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
646 #define VIC ((VIC_Type *) VIC_BASE ) /*!< VIC configuration struct */
647 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
648 #define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
649
650 /*@} */
651
652 /*******************************************************************************
653 * Hardware Abstraction Layer
654 Core Function Interface contains:
655 - Core VIC Functions
656 - Core CORET Functions
657 - Core Register Access Functions
658 ******************************************************************************/
659 /**
660 \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
661 */
662
663 /* ########################## VIC functions #################################### */
664 /**
665 \ingroup CSI_Core_FunctionInterface
666 \defgroup CSI_Core_VICFunctions VIC Functions
667 \brief Functions that manage interrupts and exceptions via the VIC.
668 @{
669 */
670
671 /* The following MACROS handle generation of the register offset and byte masks */
672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
673 #define _IR_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
675
676 extern uint32_t __Vectors[];
677
678 /**
679 \brief Enable External Interrupt
680 \details Enable a device-specific interrupt in the VIC interrupt controller.
681 \param [in] IRQn External interrupt number. Value cannot be negative.
682 */
csi_vic_enable_irq(int32_t IRQn)683 __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
684 {
685 IRQn &= 0x7FUL;
686
687 VIC->ISER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
688 #ifdef CONFIG_SYSTEM_SECURE
689 VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
690 #endif
691 }
692
693 /**
694 \brief Disable External Interrupt
695 \details Disable a device-specific interrupt in the VIC interrupt controller.
696 \param [in] IRQn External interrupt number. Value cannot be negative.
697 */
csi_vic_disable_irq(int32_t IRQn)698 __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
699 {
700 IRQn &= 0x7FUL;
701
702 VIC->ICER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
703 }
704
705 /**
706 \brief Enable External Secure Interrupt
707 \details Enable a secure device-specific interrupt in the VIC interrupt controller.
708 \param [in] IRQn External interrupt number. Value cannot be negative.
709 */
csi_vic_enable_sirq(int32_t IRQn)710 __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
711 {
712 IRQn &= 0x7FUL;
713
714 VIC->ISSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
715 }
716
717 /**
718 \brief Disable External Secure Interrupt
719 \details Disable a secure device-specific interrupt in the VIC interrupt controller.
720 \param [in] IRQn External interrupt number. Value cannot be negative.
721 */
csi_vic_disable_sirq(int32_t IRQn)722 __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
723 {
724 IRQn &= 0x7FUL;
725
726 VIC->ICSR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
727 }
728
729 /**
730 \brief Check Interrupt is Enabled or not
731 \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
732 \param [in] IRQn Interrupt number.
733 \return 0 Interrupt status is not enabled.
734 \return 1 Interrupt status is enabled.
735 */
csi_vic_get_enabled_irq(int32_t IRQn)736 __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
737 {
738 IRQn &= 0x7FUL;
739
740 return ((uint32_t)(((VIC->ISER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
741 }
742
743 /**
744 \brief Check Interrupt is Pending or not
745 \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
746 \param [in] IRQn Interrupt number.
747 \return 0 Interrupt status is not pending.
748 \return 1 Interrupt status is pending.
749 */
csi_vic_get_pending_irq(int32_t IRQn)750 __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
751 {
752 IRQn &= 0x7FUL;
753
754 return ((uint32_t)(((VIC->ISPR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
755 }
756
757 /**
758 \brief Set Pending Interrupt
759 \details Set the pending bit of an external interrupt.
760 \param [in] IRQn Interrupt number. Value cannot be negative.
761 */
csi_vic_set_pending_irq(int32_t IRQn)762 __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
763 {
764 IRQn &= 0x7FUL;
765
766 VIC->ISPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
767 }
768
769 /**
770 \brief Clear Pending Interrupt
771 \details Clear the pending bit of an external interrupt.
772 \param [in] IRQn External interrupt number. Value cannot be negative.
773 */
csi_vic_clear_pending_irq(int32_t IRQn)774 __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
775 {
776 IRQn &= 0x7FUL;
777
778 VIC->ICPR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
779 }
780
781 /**
782 \brief Check Interrupt is Wakeup or not
783 \details Read the wake up register in the VIC and returns the pending bit for the specified interrupt.
784 \param [in] IRQn Interrupt number.
785 \return 0 Interrupt is not set as wake up interrupt.
786 \return 1 Interrupt is set as wake up interrupt.
787 */
csi_vic_get_wakeup_irq(int32_t IRQn)788 __STATIC_INLINE uint32_t csi_vic_get_wakeup_irq(int32_t IRQn)
789 {
790 IRQn &= 0x7FUL;
791
792 return ((uint32_t)(((VIC->IWER[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
793 }
794
795 /**
796 \brief Set Wake up Interrupt
797 \details Set the wake up bit of an external interrupt.
798 \param [in] IRQn Interrupt number. Value cannot be negative.
799 */
csi_vic_set_wakeup_irq(int32_t IRQn)800 __STATIC_INLINE void csi_vic_set_wakeup_irq(int32_t IRQn)
801 {
802 IRQn &= 0x7FUL;
803
804 VIC->IWER[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
805 }
806
807 /**
808 \brief Clear Wake up Interrupt
809 \details Clear the wake up bit of an external interrupt.
810 \param [in] IRQn External interrupt number. Value cannot be negative.
811 */
csi_vic_clear_wakeup_irq(int32_t IRQn)812 __STATIC_INLINE void csi_vic_clear_wakeup_irq(int32_t IRQn)
813 {
814 IRQn &= 0x7FUL;
815
816 VIC->IWDR[_IR_IDX(IRQn)] = (uint32_t)(1UL << ((uint32_t)(int32_t)IRQn % 32));
817 }
818
819 /**
820 \brief Get Interrupt is Active or not
821 \details Read the active register in the VIC and returns the active bit for the device specific interrupt.
822 \param [in] IRQn Device specific interrupt number.
823 \return 0 Interrupt status is not active.
824 \return 1 Interrupt status is active.
825 \note IRQn must not be negative.
826 */
csi_vic_get_active(int32_t IRQn)827 __STATIC_INLINE uint32_t csi_vic_get_active(int32_t IRQn)
828 {
829 IRQn &= 0x7FUL;
830
831 return ((uint32_t)(((VIC->IABR[_IR_IDX(IRQn)] & (1UL << (((uint32_t)(int32_t)IRQn % 32) & 0x7FUL))) != 0UL) ? 1UL : 0UL));
832 }
833
834 /**
835 \brief Set Threshold register
836 \details set the threshold register in the VIC.
837 \param [in] VectThreshold specific vector threshold.
838 \param [in] PrioThreshold specific priority threshold.
839 */
csi_vic_set_threshold(uint32_t VectThreshold,uint32_t PrioThreshold)840 __STATIC_INLINE void csi_vic_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold)
841 {
842 VectThreshold &= 0x7FUL;
843
844 if (VectThreshold <= 31) {
845 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x3) << 6);
846 }
847
848 if (VectThreshold > 31 && VectThreshold < 96) {
849 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0x7) << 5);
850 }
851
852 if (VectThreshold > 95) {
853 VIC->IPTR = 0x80000000 | (((VectThreshold + 32) & 0xFF) << 8) | ((PrioThreshold & 0xF) << 4);
854 }
855 }
856
857 /**
858 \brief Set Interrupt Priority
859 \details Set the priority of an interrupt.
860 \note The priority cannot be set for every core interrupt.
861 \param [in] IRQn Interrupt number.
862 \param [in] priority Priority to set.
863 */
csi_vic_set_prio(int32_t IRQn,uint32_t priority)864 __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
865 {
866 VIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(VIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
867 (((priority << (8U - __VIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
868 }
869
870 /**
871 \brief Get Interrupt Priority
872 \details Read the priority of an interrupt.
873 The interrupt number can be positive to specify an external (device specific) interrupt,
874 or negative to specify an internal (core) interrupt.
875 \param [in] IRQn Interrupt number.
876 \return Interrupt Priority.
877 Value is aligned automatically to the implemented priority bits of the microcontroller.
878 */
csi_vic_get_prio(int32_t IRQn)879 __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
880 {
881 return ((uint32_t)(((VIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __VIC_PRIO_BITS)));
882 }
883
884 /**
885 \brief Set interrupt handler
886 \details Set the interrupt handler according to the interrupt num, the handler will be filled in __Vectors[].
887 \param [in] IRQn Interrupt number.
888 \param [in] handler Interrupt handler.
889 */
csi_vic_set_vector(int32_t IRQn,uint32_t handler)890 __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
891 {
892 if (IRQn >= 0 && IRQn < 128) {
893 __Vectors[32 + IRQn] = handler;
894 }
895 }
896
897 /**
898 \brief Get interrupt handler
899 \details Get the address of interrupt handler function.
900 \param [in] IRQn Interrupt number.
901 */
csi_vic_get_vector(int32_t IRQn)902 __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
903 {
904 if (IRQn >= 0 && IRQn < 128) {
905 return (uint32_t)__Vectors[32 + IRQn];
906 }
907
908 return 0;
909 }
910
911 /*@} end of CSI_Core_VICFunctions */
912
913 /* ################################## SysTick function ############################################ */
914 /**
915 \ingroup CSI_Core_FunctionInterface
916 \defgroup CSI_Core_SysTickFunctions SysTick Functions
917 \brief Functions that configure the System.
918 @{
919 */
920
921
922 /**
923 \brief CORE timer Configuration
924 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
925 Counter is in free running mode to generate periodic interrupts.
926 \param [in] ticks Number of ticks between two interrupts.
927 \param [in] IRQn core timer Interrupt number.
928 \return 0 Function succeeded.
929 \return 1 Function failed.
930 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
931 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
932 must contain a vendor-specific implementation of this function.
933 */
csi_coret_config(uint32_t ticks,int32_t IRQn)934 __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
935 {
936 if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
937 return (1UL); /* Reload value impossible */
938 }
939
940 CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
941 CORET->VAL = 0UL; /* Load the CORET Counter Value */
942 CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
943 CORET_CTRL_TICKINT_Msk |
944 CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
945 return (0UL); /* Function successful */
946 }
947
948 /**
949 \brief get CORE timer reload value
950 \return CORE timer counter value.
951 */
csi_coret_get_load(void)952 __STATIC_INLINE uint32_t csi_coret_get_load(void)
953 {
954 return CORET->LOAD;
955 }
956
957 /**
958 \brief get CORE timer counter value
959 \return CORE timer counter value.
960 */
csi_coret_get_value(void)961 __STATIC_INLINE uint32_t csi_coret_get_value(void)
962 {
963 return CORET->VAL;
964 }
965
966 /*@} end of CSI_Core_SysTickFunctions */
967
968 /* ##################################### DCC function ########################################### */
969 /**
970 \ingroup CSI_Core_FunctionInterface
971 \defgroup CSI_core_DebugFunctions HAD Functions
972 \brief Functions that access the HAD debug interface.
973 @{
974 */
975
976 /**
977 \brief HAD Send Character
978 \details Transmits a character via the HAD channel 0, and
979 \li Just returns when no debugger is connected that has booked the output.
980 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
981 \param [in] ch Character to transmit.
982 \returns Character to transmit.
983 */
csi_had_send_char(uint32_t ch)984 __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
985 {
986 DCC->DERJR = (uint8_t)ch;
987
988 return (ch);
989 }
990
991
992 /**
993 \brief HAD Receive Character
994 \details Inputs a character via the external variable \ref HAD_RxBuffer.
995 \return Received character.
996 \return -1 No character pending.
997 */
csi_had_receive_char(void)998 __STATIC_INLINE int32_t csi_had_receive_char(void)
999 {
1000 int32_t ch = -1; /* no character available */
1001
1002 if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
1003 ch = DCC->DERJW;
1004 }
1005
1006 return (ch);
1007 }
1008
1009
1010 /**
1011 \brief HAD Check Character
1012 \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
1013 \return 0 No character available.
1014 \return 1 Character available.
1015 */
csi_had_check_char(void)1016 __STATIC_INLINE int32_t csi_had_check_char(void)
1017 {
1018 return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
1019 }
1020
1021 /*@} end of CSI_core_DebugFunctions */
1022
1023 /* ########################## Cache functions #################################### */
1024 /**
1025 \ingroup CSI_Core_FunctionInterface
1026 \defgroup CSI_Core_CacheFunctions Cache Functions
1027 \brief Functions that configure Instruction and Data cache.
1028 @{
1029 */
1030
1031 /**
1032 \brief Enable I-Cache
1033 \details Turns on I-Cache
1034 */
csi_icache_enable(void)1035 __STATIC_INLINE void csi_icache_enable (void)
1036 {
1037 #if (__ICACHE_PRESENT == 1U)
1038 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1039 CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
1040 #endif
1041 }
1042
1043
1044 /**
1045 \brief Disable I-Cache
1046 \details Turns off I-Cache
1047 */
csi_icache_disable(void)1048 __STATIC_INLINE void csi_icache_disable (void)
1049 {
1050 #if (__ICACHE_PRESENT == 1U)
1051 CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
1052 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1053 #endif
1054 }
1055
1056
1057 /**
1058 \brief Invalidate I-Cache
1059 \details Invalidates I-Cache
1060 */
csi_icache_invalid(void)1061 __STATIC_INLINE void csi_icache_invalid (void)
1062 {
1063 #if (__ICACHE_PRESENT == 1U)
1064 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1065 #endif
1066 }
1067
1068
1069 /**
1070 \brief Enable D-Cache
1071 \details Turns on D-Cache
1072 \note I-Cache also turns on.
1073 */
csi_dcache_enable(void)1074 __STATIC_INLINE void csi_dcache_enable (void)
1075 {
1076 #if (__DCACHE_PRESENT == 1U)
1077 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1078 CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk & (~CACHE_CER_CFIG_Msk)); /* enable all Cache */
1079 #endif
1080 }
1081
1082
1083 /**
1084 \brief Disable D-Cache
1085 \details Turns off D-Cache
1086 \note I-Cache also turns off.
1087 */
csi_dcache_disable(void)1088 __STATIC_INLINE void csi_dcache_disable (void)
1089 {
1090 #if (__DCACHE_PRESENT == 1U)
1091 CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
1092 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1093 #endif
1094 }
1095
1096
1097 /**
1098 \brief Invalidate D-Cache
1099 \details Invalidates D-Cache
1100 \note I-Cache also invalid
1101 */
csi_dcache_invalid(void)1102 __STATIC_INLINE void csi_dcache_invalid (void)
1103 {
1104 #if (__DCACHE_PRESENT == 1U)
1105 CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
1106 #endif
1107 }
1108
1109
1110 /**
1111 \brief Clean D-Cache
1112 \details Cleans D-Cache
1113 \note I-Cache also cleans
1114 */
csi_dcache_clean(void)1115 __STATIC_INLINE void csi_dcache_clean (void)
1116 {
1117 #if (__DCACHE_PRESENT == 1U)
1118 CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
1119 #endif
1120 }
1121
1122
1123 /**
1124 \brief Clean & Invalidate D-Cache
1125 \details Cleans and Invalidates D-Cache
1126 \note I-Cache also flush.
1127 */
csi_dcache_clean_invalid(void)1128 __STATIC_INLINE void csi_dcache_clean_invalid (void)
1129 {
1130 #if (__DCACHE_PRESENT == 1U)
1131 CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
1132 #endif
1133 }
1134
1135
1136 /**
1137 \brief D-Cache Invalidate by address
1138 \details Invalidates D-Cache for the given address
1139 \param[in] addr address (aligned to 16-byte boundary)
1140 \param[in] dsize size of memory block (in number of bytes)
1141 */
csi_dcache_invalid_range(uint32_t * addr,int32_t dsize)1142 __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
1143 {
1144 #if (__DCACHE_PRESENT == 1U)
1145 int32_t op_size = dsize;
1146 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1147 int32_t linesize = 16;
1148
1149 op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1150
1151 while (op_size >= 128) {
1152 CACHE->CIR = op_addr;
1153 op_addr += linesize;
1154 CACHE->CIR = op_addr;
1155 op_addr += linesize;
1156 CACHE->CIR = op_addr;
1157 op_addr += linesize;
1158 CACHE->CIR = op_addr;
1159 op_addr += linesize;
1160 CACHE->CIR = op_addr;
1161 op_addr += linesize;
1162 CACHE->CIR = op_addr;
1163 op_addr += linesize;
1164 CACHE->CIR = op_addr;
1165 op_addr += linesize;
1166 CACHE->CIR = op_addr;
1167 op_addr += linesize;
1168
1169 op_size -= 128;
1170 }
1171
1172 while (op_size > 0) {
1173 CACHE->CIR = op_addr;
1174 op_addr += linesize;
1175 op_size -= linesize;
1176 }
1177 #endif
1178 }
1179
1180
1181 /**
1182 \brief D-Cache Clean by address
1183 \details Cleans D-Cache for the given address
1184 \param[in] addr address (aligned to 16-byte boundary)
1185 \param[in] dsize size of memory block (in number of bytes)
1186 */
csi_dcache_clean_range(uint32_t * addr,int32_t dsize)1187 __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
1188 {
1189 #if (__DCACHE_PRESENT == 1)
1190 int32_t op_size = dsize;
1191 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1192 int32_t linesize = 16;
1193
1194 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
1195
1196 while (op_size >= 128) {
1197 CACHE->CIR = op_addr;
1198 op_addr += linesize;
1199 CACHE->CIR = op_addr;
1200 op_addr += linesize;
1201 CACHE->CIR = op_addr;
1202 op_addr += linesize;
1203 CACHE->CIR = op_addr;
1204 op_addr += linesize;
1205 CACHE->CIR = op_addr;
1206 op_addr += linesize;
1207 CACHE->CIR = op_addr;
1208 op_addr += linesize;
1209 CACHE->CIR = op_addr;
1210 op_addr += linesize;
1211 CACHE->CIR = op_addr;
1212 op_addr += linesize;
1213
1214 op_size -= 128;
1215 }
1216
1217 while (op_size > 0) {
1218 CACHE->CIR = op_addr;
1219 op_addr += linesize;
1220 op_size -= linesize;
1221 }
1222 #endif
1223 }
1224
1225
1226 /**
1227 \brief D-Cache Clean and Invalidate by address
1228 \details Cleans and invalidates D_Cache for the given address
1229 \param[in] addr address (aligned to 16-byte boundary)
1230 \param[in] dsize size of memory block (in number of bytes)
1231 */
csi_dcache_clean_invalid_range(uint32_t * addr,int32_t dsize)1232 __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
1233 {
1234 #if (__DCACHE_PRESENT == 1U)
1235 int32_t op_size = dsize;
1236 uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
1237 int32_t linesize = 16;
1238
1239 op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
1240
1241 while (op_size >= 128) {
1242 CACHE->CIR = op_addr;
1243 op_addr += linesize;
1244 CACHE->CIR = op_addr;
1245 op_addr += linesize;
1246 CACHE->CIR = op_addr;
1247 op_addr += linesize;
1248 CACHE->CIR = op_addr;
1249 op_addr += linesize;
1250 CACHE->CIR = op_addr;
1251 op_addr += linesize;
1252 CACHE->CIR = op_addr;
1253 op_addr += linesize;
1254 CACHE->CIR = op_addr;
1255 op_addr += linesize;
1256 CACHE->CIR = op_addr;
1257 op_addr += linesize;
1258
1259 op_size -= 128;
1260 }
1261
1262 while (op_size > 0) {
1263 CACHE->CIR = op_addr;
1264 op_addr += linesize;
1265 op_size -= linesize;
1266 }
1267 #endif
1268 }
1269
1270 /**
1271 \brief setup cacheable range Cache
1272 \details setup Cache range
1273 */
csi_cache_set_range(uint32_t index,uint32_t baseAddr,uint32_t size,uint32_t enable)1274 __STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
1275 {
1276 CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
1277 (_VAL2FLD(CACHE_CRCR_SIZE, size)) |
1278 (_VAL2FLD(CACHE_CRCR_EN, enable)));
1279 }
1280
1281 /**
1282 \brief Enable cache profile
1283 \details Turns on Cache profile
1284 */
csi_cache_enable_profile(void)1285 __STATIC_INLINE void csi_cache_enable_profile (void)
1286 {
1287 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
1288 }
1289
1290 /**
1291 \brief Disable cache profile
1292 \details Turns off Cache profile
1293 */
csi_cache_disable_profile(void)1294 __STATIC_INLINE void csi_cache_disable_profile (void)
1295 {
1296 CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
1297 }
1298
1299 /**
1300 \brief Reset cache profile
1301 \details Reset Cache profile
1302 */
csi_cache_reset_profile(void)1303 __STATIC_INLINE void csi_cache_reset_profile (void)
1304 {
1305 CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
1306 }
1307
1308 /**
1309 \brief cache access times
1310 \details Cache access times
1311 \note every 256 access add 1.
1312 \return cache access times, actual times should be multiplied by 256
1313 */
csi_cache_get_access_time(void)1314 __STATIC_INLINE uint32_t csi_cache_get_access_time (void)
1315 {
1316 return CACHE->CPFATR;
1317 }
1318
1319 /**
1320 \brief cache miss times
1321 \details Cache miss times
1322 \note every 256 miss add 1.
1323 \return cache miss times, actual times should be multiplied by 256
1324 */
csi_cache_get_miss_time(void)1325 __STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
1326 {
1327 return CACHE->CPFMTR;
1328 }
1329
1330 /*@} end of CSI_Core_CacheFunctions */
1331
1332 /*@} end of CSI_core_DebugFunctions */
1333
1334 /* ########################## MPU functions #################################### */
1335 /**
1336 \ingroup CSI_Core_FunctionInterface
1337 \defgroup CSI_Core_MPUFunctions MPU Functions
1338 \brief Functions that configure MPU.
1339 @{
1340 */
1341
1342 typedef enum {
1343 REGION_SIZE_128B = 0x6,
1344 REGION_SIZE_256B = 0x7,
1345 REGION_SIZE_512B = 0x8,
1346 REGION_SIZE_1KB = 0x9,
1347 REGION_SIZE_2KB = 0xA,
1348 REGION_SIZE_4KB = 0xB,
1349 REGION_SIZE_8KB = 0xC,
1350 REGION_SIZE_16KB = 0xD,
1351 REGION_SIZE_32KB = 0xE,
1352 REGION_SIZE_64KB = 0xF,
1353 REGION_SIZE_128KB = 0x10,
1354 REGION_SIZE_256KB = 0x11,
1355 REGION_SIZE_512KB = 0x12,
1356 REGION_SIZE_1MB = 0x13,
1357 REGION_SIZE_2MB = 0x14,
1358 REGION_SIZE_4MB = 0x15,
1359 REGION_SIZE_8MB = 0x16,
1360 REGION_SIZE_16MB = 0x17,
1361 REGION_SIZE_32MB = 0x18,
1362 REGION_SIZE_64MB = 0x19,
1363 REGION_SIZE_128MB = 0x1A,
1364 REGION_SIZE_256MB = 0x1B,
1365 REGION_SIZE_512MB = 0x1C,
1366 REGION_SIZE_1GB = 0x1D,
1367 REGION_SIZE_2GB = 0x1E,
1368 REGION_SIZE_4GB = 0x1F
1369 } region_size_e;
1370
1371 typedef enum {
1372 AP_BOTH_INACCESSIBLE = 0,
1373 AP_SUPER_RW_USER_INACCESSIBLE,
1374 AP_SUPER_RW_USER_RDONLY,
1375 AP_BOTH_RW
1376 } access_permission_e;
1377
1378 typedef struct {
1379 uint32_t nx: 1; /* instruction fetched execution */
1380 access_permission_e ap: 2; /* super user and normal user access.*/
1381 uint32_t s: 1; /* security */
1382 } mpu_region_attr_t;
1383
1384 /**
1385 \brief enable mpu
1386 \details
1387 */
csi_mpu_enable(void)1388 __STATIC_INLINE void csi_mpu_enable(void)
1389 {
1390 __set_CCR(__get_CCR() | CCR_MP_Msk);
1391 }
1392
1393 /**
1394 \brief disable mpu
1395 \details
1396 */
csi_mpu_disable(void)1397 __STATIC_INLINE void csi_mpu_disable(void)
1398 {
1399 __set_CCR(__get_CCR() & (~CCR_MP_Msk));
1400 }
1401
1402 /**
1403 \brief configure memory protected region.
1404 \details
1405 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1406 \param [in] base_addr base address must be aligned with page size.
1407 \param [in] size \ref region_size_e. memory protected region size.
1408 \param [in] attr \ref region_size_t. memory protected region attribute.
1409 \param [in] enable enable or disable memory protected region.
1410 */
csi_mpu_config_region(uint32_t idx,uint32_t base_addr,region_size_e size,mpu_region_attr_t attr,uint32_t enable)1411 __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
1412 mpu_region_attr_t attr, uint32_t enable)
1413 {
1414 CAPR_Type capr;
1415 PACR_Type pacr;
1416 PRSR_Type prsr;
1417
1418 if (idx > 7) {
1419 return;
1420 }
1421
1422 capr.w = __get_CAPR();
1423 pacr.w = __get_PACR();
1424 prsr.w = __get_PRSR();
1425
1426 pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0x3FFFFFF);
1427
1428 prsr.b.RID = idx;
1429 __set_PRSR(prsr.w);
1430
1431 if (size != REGION_SIZE_128B) {
1432 pacr.w &= ~(((1u << (size -6)) - 1) << 7);
1433 }
1434
1435 pacr.b.size = size;
1436
1437 capr.w &= ~((0x1 << idx) | (0x3 << (idx * 2 + 8)) | (0x1 << (idx + 24)));
1438 capr.w = (capr.w | (attr.nx << idx) | (attr.ap << (idx * 2 + 8)) | (attr.s << (idx + 24)));
1439 __set_CAPR(capr.w);
1440
1441 pacr.b.E = enable;
1442 __set_PACR(pacr.w);
1443 }
1444
1445 /**
1446 \brief enable mpu region by idx.
1447 \details
1448 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1449 */
csi_mpu_enable_region(uint32_t idx)1450 __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
1451 {
1452 if (idx > 7) {
1453 return;
1454 }
1455
1456 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
1457 __set_PACR(__get_PACR() | PACR_E_Msk);
1458 }
1459
1460 /**
1461 \brief disable mpu region by idx.
1462 \details
1463 \param [in] idx memory protected region (0, 1, 2, ..., 7).
1464 */
csi_mpu_disable_region(uint32_t idx)1465 __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
1466 {
1467 if (idx > 7) {
1468 return;
1469 }
1470
1471 __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
1472 __set_PACR(__get_PACR() & (~PACR_E_Msk));
1473 }
1474
1475 /*@} end of CSI_Core_MMUFunctions */
1476
1477
1478 /* ################################## IRQ Functions ############################################ */
1479
1480 /**
1481 \brief Save the Irq context
1482 \details save the psr result before disable irq.
1483 */
csi_irq_save(void)1484 __STATIC_INLINE uint32_t csi_irq_save(void)
1485 {
1486 uint32_t result;
1487 result = __get_PSR();
1488 __disable_irq();
1489 return(result);
1490 }
1491
1492 /**
1493 \brief Restore the Irq context
1494 \details restore saved primask state.
1495 \param [in] irq_state psr irq state.
1496 */
csi_irq_restore(uint32_t irq_state)1497 __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
1498 {
1499 __set_PSR(irq_state);
1500 }
1501
1502 /*@} end of IRQ Functions */
1503
1504 /**
1505 \brief System Reset
1506 \details Initiates a system reset request to reset the MCU.
1507 */
csi_system_reset(void)1508 __STATIC_INLINE void csi_system_reset(void)
1509 {
1510 CHR_Type chr;
1511
1512 chr.w = __get_CHR();
1513 #ifdef __RESET_CONST
1514 chr.b.SRST_VAL = __RESET_CONST;
1515 #else
1516 chr.b.SRST_VAL = 0xABCD;
1517 #endif
1518
1519 __DSB(); /* Ensure all outstanding memory accesses included
1520 buffered write are completed before reset */
1521 __set_CHR(chr.w);
1522
1523 __DSB(); /* Ensure completion of memory access */
1524
1525 for(;;) /* wait until reset */
1526 {
1527 __NOP();
1528 }
1529 }
1530
1531 /* ################################## Old Interfaces ############################################ */
1532
1533 /* These interfaces are deprecated */
1534 #define NVIC_EnableIRQ(IRQn) csi_vic_enable_irq(IRQn)
1535 #define NVIC_DisableIRQ(IRQn) csi_vic_disable_irq(IRQn)
1536 #define NVIC_GetPendingIRQ(IRQn) csi_vic_get_pending_irq(IRQn)
1537 #define NVIC_SetPendingIRQ(IRQn) csi_vic_set_pending_irq(IRQn)
1538 #define NVIC_ClearPendingIRQ(IRQn) csi_vic_clear_pending_irq(IRQn)
1539 #define NVIC_GetWakeupIRQ(IRQn) csi_vic_get_wakeup_irq(IRQn)
1540 #define NVIC_SetWakeupIRQ(IRQn) csi_vic_set_wakeup_irq(IRQn)
1541 #define NVIC_ClearWakeupIRQ(IRQn) csi_vic_clear_wakeup_irq(IRQn)
1542 #define NVIC_GetActive(IRQn) csi_vic_get_active(IRQn)
1543 #define NVIC_SetThreshold(VectThreshold, PrioThreshold) csi_vic_set_threshold(VectThreshold, PrioThreshold)
1544 #define NVIC_SetPriority(IRQn, priority) csi_vic_set_prio(IRQn, priority)
1545 #define NVIC_GetPriority(IRQn) csi_vic_get_prio(IRQn)
1546 #define NVIC_SystemReset() csi_system_reset()
1547
1548 #define SysTick_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1549 #define CORET_Config(ticks) csi_coret_config(ticks, CORET_IRQn)
1550
1551 #define HAD_SendChar(ch) csi_had_sned_char(ch)
1552 #define HAD_ReceiveChar() csi_had_receive_char()
1553 #define HAD_CheckChar() csi_had_check_char()
1554
1555 /*@} end of Old Interfaces */
1556
1557 #ifdef __cplusplus
1558 }
1559 #endif
1560
1561 #endif /* __CORE_802_H_DEPENDANT */
1562
1563 #endif /* __CSI_GENERIC */
1564