1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * Description: diag mem adapt
15 * This file should be changed only infrequently and with great care.
16 */
17
18 #ifdef CONFIG_REG_WHITELIST
19 #include "diag_adapt_cmd_mem.h"
20 #include "soc_errno.h"
21 #endif
22 #include "diag_cmd_mem_read_write.h"
23
24 typedef struct diag_mem_config {
25 uintptr_t start_addr;
26 uintptr_t end_addr;
27 } diag_mem_config_t;
28
29 const diag_mem_config_t g_mem_config[] = {
30 { 0x44210060, 0x44210064 }, // DURATION调整寄存器
31 { 0x442100D0, 0x442100D4 }, // TXOP结束发送CF END的最小时间
32 { 0x44210138, 0x4421013C }, // 旁路控制寄存器
33 { 0x44210064, 0x4421006C }, // 接收Duration最大值
34 { 0x44210098, 0x442100A0 }, // AC队列/MU时各队列的竞争窗口
35 { 0x442100B0, 0x442100B8 }, // AC各队列TXOP LIMIT
36 { 0x4400D868, 0x4400D880 }, // SFC
37 { 0x00100000, 0x0017FFFF }, // ITCM
38 { 0x00180000, 0x001C7FFF }, // DTCM
39 { 0x00200000, 0x00800000 }, // FLASH
40 { 0x00A00000, 0x00A987FF } // RAM
41 };
42
diag_permit_check(uintptr_t start_addr,uintptr_t end_addr)43 static bool diag_permit_check(uintptr_t start_addr, uintptr_t end_addr)
44 {
45 bool ret = false;
46 uint32_t loop;
47
48 for (loop = 0; loop < sizeof(g_mem_config) / sizeof(diag_mem_config_t); loop++) {
49 if ((g_mem_config[loop].start_addr <= start_addr) && (g_mem_config[loop].end_addr >= end_addr)) {
50 ret = true;
51 break;
52 }
53 }
54 return ret;
55 }
56
57 #ifdef CONFIG_REG_WHITELIST
reg_rw_check_addr(osal_u32 start_addr,osal_u32 bytes_cnt)58 osal_s32 reg_rw_check_addr(osal_u32 start_addr, osal_u32 bytes_cnt)
59 {
60 bool ret = diag_permit_check(start_addr, start_addr + bytes_cnt);
61 if (ret) {
62 return EXT_SUCCESS;
63 } else {
64 return EXT_FAILURE;
65 }
66 }
67 #endif
68
diag_cmd_permit_read(uintptr_t start_addr,uintptr_t end_addr)69 bool diag_cmd_permit_read(uintptr_t start_addr, uintptr_t end_addr)
70 {
71 return diag_permit_check(start_addr, end_addr);
72 }
73
diag_cmd_permit_write(uintptr_t start_addr,uintptr_t end_addr)74 bool diag_cmd_permit_write(uintptr_t start_addr, uintptr_t end_addr)
75 {
76 return diag_permit_check(start_addr, end_addr);
77 }
78