1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides dma port \n 16 * 17 * History: \n 18 * 2022-10-16， Create file. \n 19 */ 20 21 #ifndef DMA_PORTING_H 22 #define DMA_PORTING_H 23 24 #include <stdint.h> 25 #include <stdbool.h> 26 #include "dma.h" 27 28 #ifdef __cplusplus 29 #if __cplusplus 30 extern "C" { 31 #endif /* __cplusplus */ 32 #endif /* __cplusplus */ 33 34 /** 35 * @defgroup drivers_port_dma_v151 DMA V151 36 * @ingroup drivers_port_dma 37 * @{ 38 */ 39 40 #define S_DMA_CHANNEL_MAX_NUM 4 /*!< Max number of SM_DMA available. */ 41 #define B_DMA_CHANNEL_MAX_NUM 8 /*!< Max number of M_DMA available. */ 42 43 #define S_MGPIO33 33 44 #define S_MGPIO34 34 45 46 #define DMA_CHANNEL_MAX_NUM (S_DMA_CHANNEL_MAX_NUM + B_DMA_CHANNEL_MAX_NUM) 47 48 /** 49 * @brief DMA channel ID. 50 */ 51 typedef enum { 52 DMA_CHANNEL_0, /*!< DMA channel 0. */ 53 DMA_CHANNEL_1, /*!< DMA channel 1. */ 54 DMA_CHANNEL_2, /*!< DMA channel 2. */ 55 DMA_CHANNEL_3, /*!< DMA channel 3. */ 56 DMA_CHANNEL_4, /*!< DMA channel 4. */ 57 DMA_CHANNEL_5, /*!< DMA channel 5. */ 58 DMA_CHANNEL_6, /*!< DMA channel 6. */ 59 DMA_CHANNEL_7, /*!< DMA channel 7. */ 60 DMA_CHANNEL_NONE = DMA_CHANNEL_MAX_NUM 61 } dma_channel_t; 62 63 /** 64 * @brief DMA handshaking source select. 65 */ 66 typedef enum { 67 HAL_DMA_HANDSHAKING_TIE0, 68 HAL_DMA_HANDSHAKING_UART_L_TX, 69 HAL_DMA_HANDSHAKING_UART_L_RX, 70 HAL_DMA_HANDSHAKING_UART_H0_TX, 71 HAL_DMA_HANDSHAKING_UART_H0_RX, 72 HAL_DMA_HANDSHAKING_UART_H1_TX, 73 HAL_DMA_HANDSHAKING_UART_H1_RX, 74 HAL_DMA_HANDSHAKING_SPI_MS0_TX, 75 HAL_DMA_HANDSHAKING_SPI_MS0_RX, 76 HAL_DMA_HANDSHAKING_QSPI0_2CS_TX, 77 HAL_DMA_HANDSHAKING_QSPI0_2CS_RX, 78 HAL_DMA_HANDSHAKING_I2S_TX, 79 HAL_DMA_HANDSHAKING_I2S_RX, 80 HAL_DMA_HANDSHAKING_SPI_MS1_TX, 81 HAL_DMA_HANDSHAKING_SPI_MS1_RX, 82 HAL_DMA_HANDSHAKING_SPI_M_TX, 83 HAL_DMA_HANDSHAKING_SPI_M_RX, 84 HAL_DMA_HANDSHAKING_OPI_TX, 85 HAL_DMA_HANDSHAKING_OPI_RX, 86 HAL_DMA_HANDSHAKING_QSPI1_2CS_TX, 87 HAL_DMA_HANDSHAKING_QSPI1_2CS_RX, 88 HAL_DMA_HANDSHAKING_QSPI2_1CS_TX, 89 HAL_DMA_HANDSHAKING_QSPI2_1CS_RX, 90 HAL_DMA_HANDSHAKING_SPI3_M_TX, 91 HAL_DMA_HANDSHAKING_SPI3_M_RX, 92 HAL_DMA_HANDSHAKING_QSPI3_1CS_TX, 93 HAL_DMA_HANDSHAKING_QSPI3_1CS_RX, 94 HAL_DMA_HANDSHAKING_SPI4_S_RX, 95 HAL_DMA_HANDSHAKING_SPI4_S_TX, 96 HAL_MDMA_HANDSHAKING_MAX_NUM, 97 /* SMDMA */ 98 HAL_DMA_HANDSHAKING_SDMA = HAL_MDMA_HANDSHAKING_MAX_NUM, 99 HAL_DMA_HANDSHAKING_I2C0_TX = HAL_DMA_HANDSHAKING_SDMA + 0, 100 HAL_DMA_HANDSHAKING_I2C0_RX, 101 HAL_DMA_HANDSHAKING_I2C1_TX, 102 HAL_DMA_HANDSHAKING_I2C1_RX, 103 HAL_DMA_HANDSHAKING_I2C2_TX, 104 HAL_DMA_HANDSHAKING_I2C2_RX, 105 HAL_DMA_HANDSHAKING_I2C3_TX, 106 HAL_DMA_HANDSHAKING_I2C3_RX, 107 HAL_DMA_HANDSHAKING_IR_TX, 108 HAL_DMA_HANDSHAKING_IR_RX, 109 HAL_DMA_HANDSHAKING_I2C4_TX, 110 HAL_DMA_HANDSHAKING_I2C4_RX, 111 HAL_DMA_HANDSHAKING_I2C5_TX, 112 HAL_DMA_HANDSHAKING_I2C5_RX, 113 HAL_DMA_HANDSHAKING_I2C6_TX, 114 HAL_DMA_HANDSHAKING_I2C6_RX, 115 HAL_DMA_HANDSHAKING_MAX_NUM 116 } hal_dma_handshaking_source_t; 117 118 119 /** 120 * @brief DMA Hardshaking channel. 121 */ 122 typedef enum hal_dma_hardshaking_channel { 123 HAL_DMA_HARDSHAKING_CHANNEL_0, 124 HAL_DMA_HARDSHAKING_CHANNEL_1, 125 HAL_DMA_HARDSHAKING_CHANNEL_2, 126 HAL_DMA_HARDSHAKING_CHANNEL_3, 127 HAL_DMA_HARDSHAKING_CHANNEL_4, 128 HAL_DMA_HARDSHAKING_CHANNEL_5, 129 HAL_DMA_HARDSHAKING_CHANNEL_6, 130 HAL_DMA_HARDSHAKING_CHANNEL_7, 131 HAL_DMA_HARDSHAKING_CHANNEL_MAX_NUM, 132 HAL_DMA_HARDSHAKING_CHANNEL_NONE = HAL_DMA_HARDSHAKING_CHANNEL_MAX_NUM 133 } hal_dma_hardshaking_channel_t; 134 135 extern uintptr_t g_dma_base_addr; 136 137 /** 138 * @brief Register the interrupt of dma. 139 */ 140 void dma_port_register_irq(void); 141 142 /** 143 * @brief Unregister the interrupt of dma. 144 */ 145 void dma_port_unregister_irq(void); 146 147 /** 148 * @brief Set the channel status of handshaking. 149 * @param [in] channel The handshaking select. For details, see @ref hal_dma_handshaking_source_t. 150 * @param [in] on Set or clear. 151 */ 152 void dma_port_set_handshaking_channel_status(hal_dma_handshaking_source_t channel, bool on); 153 154 /** 155 * @brief add sleep veto before dma transfer. 156 */ 157 void dma_port_add_sleep_veto(void); 158 159 /** 160 * @brief remove sleep veto after dma transfer. 161 */ 162 void dma_port_remove_sleep_veto(void); 163 164 /** 165 * @} 166 */ 167 168 #ifdef __cplusplus 169 #if __cplusplus 170 } 171 #endif /* __cplusplus */ 172 #endif /* __cplusplus */ 173 174 #endif