1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __DRV_HDMI_FRL_H__ 19 #define __DRV_HDMI_FRL_H__ 20 21 #include "hi_type.h" 22 #include "drv_hdmi_common.h" 23 #include "drv_hdmi_dfm.h" 24 25 typedef enum { 26 HDMI_FRL_TRAIN_STEP_READY_CHECK, // LTS:2 27 HDMI_FRL_TRAIN_STEP_TRAIN_START, // LTS:3 28 HDMI_FRL_TRAIN_STEP_RESULT_CHECK, // LTS:3 29 HDMI_FRL_TRAIN_STEP_RATE_CHANGE, // LTS:4 30 HDMI_FRL_TRAIN_STEP_RESULT_HANDLE, // LTS:P 31 HDMI_FRL_TRAIN_STEP_RETRAIN_CHECK, // LTS:P 32 HDMI_FRL_TRAIN_STEP_STOP, 33 HDMI_FRL_TRAIN_STEP_BUTT 34 } hdmi_frl_train_step; 35 36 typedef enum { 37 HDMI_FRL_FAIL_NONE, 38 HDMI_FRL_FAIL_TMDS, 39 HDMI_FRL_FAIL_NOTIFY, 40 HDMI_FRL_FAIL_BUTT 41 } hdmi_frl_fail_strategy; 42 43 typedef enum { 44 HDMI_FRL_STRATEGY_MODE_1, 45 HDMI_FRL_STRATEGY_MODE_2, 46 HDMI_FRL_STRATEGY_MODE_3, 47 HDMI_FRL_STRATEGY_MODE_BUTT 48 } hdmi_frl_strategy_mode; 49 50 typedef enum { 51 HDMI_FRL_RATE_SELECT_LITTLE, 52 HDMI_FRL_RATE_SELECT_BIG, 53 HDMI_FRL_RATE_SELECT_BUTT 54 } hdmi_frl_rate_select; 55 56 typedef enum { 57 DFM_BIT_RATE_3 = 3, 58 DFM_BIT_RATE_6 = 6, 59 DFM_BIT_RATE_8 = 8, 60 DFM_BIT_RATE_10 = 10, 61 DFM_BIT_RATE_12 = 12 62 } dfm_bit_rate_val; 63 64 typedef enum { 65 DFM_COLOR_DEPTH_8 = 8, 66 DFM_COLOR_DEPTH_10 = 10, 67 DFM_COLOR_DEPTH_12 = 12, 68 DFM_COLOR_DEPTH_16 = 16 69 } dfm_color_depth; 70 71 typedef enum { 72 DFM_PIXEL_FORMAT_MODE_0, 73 DFM_PIXEL_FORMAT_MODE_1, 74 DFM_PIXEL_FORMAT_MODE_2, 75 DFM_PIXEL_FORMAT_MODE_3 76 } dfm_pixel_format_mode; 77 78 typedef enum { 79 AUDIO_SAMPLE_RATE_UNKNOWN, 80 AUDIO_SAMPLE_RATE_8K = 8000, 81 AUDIO_SAMPLE_RATE_11K = 11000, 82 AUDIO_SAMPLE_RATE_12K = 12000, 83 AUDIO_SAMPLE_RATE_16K = 16000, 84 AUDIO_SAMPLE_RATE_22K = 22000, 85 AUDIO_SAMPLE_RATE_24K = 24000, 86 AUDIO_SAMPLE_RATE_32K = 32000, 87 AUDIO_SAMPLE_RATE_44K = 44100, 88 AUDIO_SAMPLE_RATE_48K = 48000, 89 AUDIO_SAMPLE_RATE_88K = 88000, 90 AUDIO_SAMPLE_RATE_96K = 96000, 91 AUDIO_SAMPLE_RATE_176K = 176000, 92 AUDIO_SAMPLE_RATE_192K = 192000, 93 AUDIO_SAMPLE_RATE_768K = 768000, 94 AUDIO_SAMPLE_RATE_BUTT 95 } hdmi_frl_info_rate; 96 97 typedef struct { 98 hi_bool start_mach; 99 hi_u64 start_time; 100 hi_u32 wait_ready_ms; 101 hi_u32 wait_handle_ms; 102 hi_u32 wait_retrain_ms; 103 hi_u32 train_timeout; 104 hdmi_frl_train_step train_status; 105 hdmi_frl_mach_mode mach_mode; 106 frl_sw_train_mode sw_train_mode; 107 } hdmi_frl_state_mach_info; 108 109 typedef struct { 110 hi_u8 max_rate; 111 hi_u8 min_rate; 112 hi_u8 cur_rate; 113 hi_u8 debug_rate; 114 } hdmi_frl_rate_info; 115 116 typedef struct { 117 hi_bool start; 118 hi_bool dsc_enable; 119 hi_bool scdc_present; 120 hi_bool cts_mode; 121 hi_bool frl_reset; 122 hi_bool work_en; 123 hi_u32 tmds_clk; 124 hi_u32 fail_count; 125 hi_u32 max_fail_times; 126 hi_u32 bypass; 127 hdmi_frl_mode mode; 128 hdmi_frl_strategy_mode strategy_mode; 129 hdmi_frl_rate_select rate_select; 130 hdmi_frl_state_mach_info state_mach_info; 131 hdmi_frl_rate_info rate_info; 132 hdmi_frl_train train_status; 133 hdmi_frl_fail_strategy fail_strategy; 134 hdmi_txfff_mode aen_cur_tx_ffe[4]; 135 } hdmi_frl_info; 136 137 typedef struct { 138 hdmi_frl_mode hdmi_mode; 139 hdmi_work_mode rate; 140 } hdmi_frl_debug; 141 142 typedef enum { 143 FRL_BYPASS_READY_CHECK = 0x1, 144 FRL_BYPASS_RESULT_CHECK = 0x2, 145 FRL_BYPASS_RETRAIN_CHECK = 0x4 146 } hdmi_frl_bypass; 147 148 typedef struct { 149 hi_u32 addr; 150 hi_u32 value; 151 } frl_rx_crc_check; 152 153 hi_void drv_hdmi_frl_mach_init(hdmi_device_id hdmi_id); 154 155 hi_void drv_hdmi_frl_enable(hdmi_device_id hdmi_id, hi_bool enable); 156 157 hi_s32 drv_hdmi_frl_mode_strategy(hdmi_device_id hdmi_id); 158 159 hi_void drv_hdmi_frl_train_mach(hdmi_device_id hdmi_id); 160 161 hi_s32 drv_hdmi_frl_mode_change(hdmi_device_id hdmi_id, const hdmi_frl_debug *debug); 162 163 #endif /* __DRV_HDMI_FRL_H__ */ 164 165