1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: cipher driver common header. \n 16 * 17 * History: \n 18 * 2023-03-22, Create file. \n 19 */ 20 #ifndef DRV_INNER_H 21 #define DRV_INNER_H 22 23 #include "crypto_hash_struct.h" 24 #include "crypto_kdf_struct.h" 25 #include "crypto_symc_struct.h" 26 #include "crypto_pke_struct.h" 27 28 #ifdef __cplusplus 29 #if __cplusplus 30 extern "C" { 31 #endif /* __cplusplus */ 32 #endif /* __cplusplus */ 33 34 typedef struct { 35 td_u8 mac[CRYPTO_IV_LEN_IN_BYTES]; 36 td_u32 mac_length; 37 td_u8 tail[CRYPTO_IV_LEN_IN_BYTES]; 38 td_u32 tail_length; 39 } crypto_symc_mac_ctx; 40 41 typedef struct { 42 td_u8 iv[CRYPTO_IV_LEN_IN_BYTES]; 43 td_u32 iv_length; 44 td_u32 chn_num; 45 td_phys_addr_t aad_phys; 46 td_u8 *aad_virt; 47 td_u32 aad_len; 48 crypto_symc_alg symc_alg; 49 crypto_symc_work_mode work_mode; 50 crypto_symc_key_length symc_key_length; 51 td_u32 last_pattern_len; 52 union { 53 crypto_symc_config_aes_ccm_gcm ccm_config; 54 } param; 55 /* 56 * For CBC_MAC, store data copy; 57 * For CCM, store N + ccm_header + ccm_padding 58 * For GCM, store aad_padding + clen 59 */ 60 td_u8 *dma_addr; 61 td_u32 dma_size; 62 td_u32 data_len; /* For CCM/GCM. */ 63 td_u32 processed_len; /* For CCM/GCM. */ 64 td_u8 tail[CRYPTO_AES_BLOCK_SIZE_IN_BYTES]; 65 td_u32 tail_length; 66 td_bool is_create_keyslot; 67 td_handle keyslot_handle; 68 td_bool is_open; 69 td_bool is_config; 70 td_bool is_attached; 71 td_u32 iv_change_flag; 72 #if defined(CRYPTO_CTR_NON_ALIGN_SUPPORT) 73 td_u32 ctr_offset; 74 td_u32 ctr_used; 75 td_u8 ctr_last_block[CRYPTO_AES_BLOCK_SIZE_IN_BYTES]; 76 #endif 77 } drv_symc_context_t; 78 79 td_s32 drv_cipher_pke_clean_ram(void); 80 81 td_s32 drv_cipher_pke_mul_dot(const drv_pke_ecc_curve *ecc, const drv_pke_data *k, const drv_pke_ecc_point *p, 82 const drv_pke_ecc_point *r); 83 84 td_s32 drv_cipher_pke_add_dot(const drv_pke_ecc_curve *ecc, const drv_pke_ecc_point *s, const drv_pke_ecc_point *r, 85 const drv_pke_ecc_point *c); 86 87 td_s32 drv_cipher_pke_mg_mul_dot(const drv_pke_data *k, const drv_pke_data *U, const drv_pke_data *p, 88 const drv_pke_data *a24, const drv_pke_data *rx); 89 90 td_s32 drv_cipher_pke_ed_mul_dot(const drv_pke_data *k, const drv_pke_ecc_point *U, const drv_pke_data *p, 91 const drv_pke_ecc_point *r); 92 93 td_s32 drv_cipher_pke_ed_add_dot(const drv_pke_ecc_curve *ecc, const drv_pke_ecc_point *s, 94 const drv_pke_ecc_point *r, const drv_pke_ecc_point *c); 95 96 td_s32 drv_cipher_pke_calc_hash(const drv_pke_data* arr, td_u32 arr_len, const drv_pke_hash_type hash_type, 97 drv_pke_data *hash); 98 99 drv_symc_context_t *inner_get_symc_ctx(td_handle symc_handle); 100 101 const td_u32 *drv_hash_get_state_iv(crypto_hash_type hash_type, td_u32 *iv_size); 102 103 td_s32 inner_hash_drv_handle_chk(td_handle hash_handle); 104 105 td_s32 inner_hash_start_param_chk(td_handle *drv_hash_handle, const crypto_hash_attr *hash_attr); 106 107 td_s32 inner_pbkdf2_param_chk(const crypto_kdf_pbkdf2_param *param, const td_u8 *out, td_u32 out_len); 108 109 td_s32 inner_drv_symc_crypto_chk(td_handle symc_handle, const crypto_buf_attr *src_buf, 110 const crypto_buf_attr *dst_buf, td_u32 length); 111 112 td_s32 inner_symc_drv_handle_chk(td_handle symc_handle); 113 114 td_s32 inner_drv_get_mac_ctx(td_handle symc_handle, crypto_symc_mac_ctx *mac_ctx); 115 116 td_s32 inner_drv_set_mac_ctx(td_handle symc_handle, const crypto_symc_mac_ctx *mac_ctx); 117 118 td_s32 inner_symc_cfg_param_check(const crypto_symc_ctrl_t *symc_ctrl); 119 120 121 typedef struct { 122 td_u8 *iv0; 123 td_u32 iv0_length; 124 td_u8 *iv_mac; 125 td_u32 iv_mac_length; 126 td_u32 data_length; 127 td_u32 processed_length; 128 td_u32 aad_len; 129 } drv_symc_ex_context_t; 130 131 td_s32 inner_drv_symc_get_iv0(td_handle symc_handle, td_u8 *iv0, td_u32 iv0_length); 132 133 td_s32 inner_drv_symc_get_iv_mac(td_handle symc_handle, td_u8 *iv_mac, td_u32 iv_mac_length); 134 135 td_s32 inner_drv_symc_ex_restore(td_handle symc_handle, const drv_symc_ex_context_t *symc_ex_ctx); 136 137 td_s32 inner_drv_symc_set_ctr_block(td_handle symc_handle, const td_u8 *block, td_u32 block_size, td_u32 ctr_offset); 138 139 td_s32 inner_drv_symc_get_ctr_block(td_handle symc_handle, td_u8 *block, td_u32 block_size, td_u32 *ctr_offset); 140 141 #ifdef __cplusplus 142 #if __cplusplus 143 } 144 #endif /* __cplusplus */ 145 #endif /* __cplusplus */ 146 147 #endif