1 /** 2 * Copyright 2024 Huawei Technologies Co., Ltd 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef MINDSPORE_CCSRC_FRONTEND_PARALLEL_PIPELINE_TRANSFORMER_GPIPE_INTERLEAVE_SCHEDULER_H_ 18 #define MINDSPORE_CCSRC_FRONTEND_PARALLEL_PIPELINE_TRANSFORMER_GPIPE_INTERLEAVE_SCHEDULER_H_ 19 20 #include <set> 21 #include <utility> 22 #include <string> 23 #include <memory> 24 #include <vector> 25 #include "ir/value.h" 26 #include "ir/graph_utils.h" 27 #include "base/base.h" 28 #include "utils/hash_map.h" 29 #include "frontend/parallel/pipeline_transformer/pipeline_scheduler.h" 30 31 namespace mindspore { 32 namespace parallel { 33 class GpipeInterleavedScheduler : public PipelineScheduler { 34 public: GpipeInterleavedScheduler(const FuncGraphManagerPtr & manager,const FuncGraphPtr & root,int64_t stage,int64_t stage_num)35 GpipeInterleavedScheduler(const FuncGraphManagerPtr &manager, const FuncGraphPtr &root, int64_t stage, 36 int64_t stage_num) 37 : PipelineScheduler(manager, root, stage, stage_num) {} 38 virtual ~GpipeInterleavedScheduler() = default; 39 40 void GetBorderNode() override; 41 void Reorder() override; 42 43 private: 44 std::vector<BorderPair> SortBetweenMicro(const std::vector<Border> &borders, bool is_backward); 45 void GetBackwardBorderNode(const CNodePtr &cnode); 46 void ForwardReorder(size_t bias, int64_t flag); 47 AbstractBasePtr GenerateTupleAbstract(const std::vector<AnfNodePtr> &nodes); 48 void OptimizerShardCommReorder(); 49 std::vector<Border> fwd_begin_; 50 std::vector<Border> fwd_end_; 51 std::vector<Border> bwd_begin_; 52 std::vector<Border> bwd_end_; 53 std::vector<Border> fwd_cell_; 54 std::vector<Border> bwd_cell_; 55 std::vector<Border> fwd_params_; 56 std::vector<Border> bwd_params_; 57 }; 58 } // namespace parallel 59 } // namespace mindspore 60 #endif // MINDSPORE_CCSRC_FRONTEND_PARALLEL_PIPELINE_TRANSFORMER_GPIPE_INTERLEAVE_SCHEDULER_H_ 61