1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 ************************************************************************************************************************ 11 * @file gfx10addrlib.h 12 * @brief Contains the Gfx10Lib class definition. 13 ************************************************************************************************************************ 14 */ 15 16 #ifndef __GFX10_ADDR_LIB_H__ 17 #define __GFX10_ADDR_LIB_H__ 18 19 #include "addrlib2.h" 20 #include "coord.h" 21 #include "gfx10SwizzlePattern.h" 22 23 namespace Addr 24 { 25 namespace V2 26 { 27 28 /** 29 ************************************************************************************************************************ 30 * @brief GFX10 specific settings structure. 31 ************************************************************************************************************************ 32 */ 33 struct Gfx10ChipSettings 34 { 35 struct 36 { 37 UINT_32 reserved1 : 32; 38 39 // Misc configuration bits 40 UINT_32 isDcn20 : 1; // If using DCN2.0 41 UINT_32 supportRbPlus : 1; 42 UINT_32 dsMipmapHtileFix : 1; 43 UINT_32 dccUnsup3DSwDis : 1; 44 UINT_32 reserved2 : 28; 45 }; 46 }; 47 48 /** 49 ************************************************************************************************************************ 50 * @brief GFX10 data surface type. 51 ************************************************************************************************************************ 52 */ 53 enum Gfx10DataType 54 { 55 Gfx10DataColor, 56 Gfx10DataDepthStencil, 57 Gfx10DataFmask 58 }; 59 60 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR); 61 62 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 63 (1u << ADDR_SW_256B_D); 64 65 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 66 (1u << ADDR_SW_4KB_D) | 67 (1u << ADDR_SW_4KB_S_X) | 68 (1u << ADDR_SW_4KB_D_X); 69 70 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 71 (1u << ADDR_SW_64KB_D) | 72 (1u << ADDR_SW_64KB_S_T) | 73 (1u << ADDR_SW_64KB_D_T) | 74 (1u << ADDR_SW_64KB_Z_X) | 75 (1u << ADDR_SW_64KB_S_X) | 76 (1u << ADDR_SW_64KB_D_X) | 77 (1u << ADDR_SW_64KB_R_X); 78 79 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) | 80 (1u << ADDR_SW_VAR_R_X); 81 82 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 83 (1u << ADDR_SW_VAR_Z_X); 84 85 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) | 86 (1u << ADDR_SW_4KB_S) | 87 (1u << ADDR_SW_64KB_S) | 88 (1u << ADDR_SW_64KB_S_T) | 89 (1u << ADDR_SW_4KB_S_X) | 90 (1u << ADDR_SW_64KB_S_X); 91 92 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 93 (1u << ADDR_SW_4KB_D) | 94 (1u << ADDR_SW_64KB_D) | 95 (1u << ADDR_SW_64KB_D_T) | 96 (1u << ADDR_SW_4KB_D_X) | 97 (1u << ADDR_SW_64KB_D_X); 98 99 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 100 (1u << ADDR_SW_VAR_R_X); 101 102 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 103 (1u << ADDR_SW_4KB_D_X) | 104 (1u << ADDR_SW_64KB_Z_X) | 105 (1u << ADDR_SW_64KB_S_X) | 106 (1u << ADDR_SW_64KB_D_X) | 107 (1u << ADDR_SW_64KB_R_X) | 108 Gfx10BlkVarSwModeMask; 109 110 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 111 (1u << ADDR_SW_64KB_D_T); 112 113 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask | 114 Gfx10TSwModeMask; 115 116 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask | 117 Gfx10RenderSwModeMask | 118 Gfx10ZSwModeMask; 119 120 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask | 121 Gfx10Blk256BSwModeMask | 122 Gfx10Blk4KBSwModeMask | 123 Gfx10Blk64KBSwModeMask | 124 Gfx10BlkVarSwModeMask; 125 126 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) | 127 (1u << ADDR_SW_4KB_S) | 128 (1u << ADDR_SW_64KB_S) | 129 (1u << ADDR_SW_64KB_S_T) | 130 (1u << ADDR_SW_4KB_S_X) | 131 (1u << ADDR_SW_64KB_Z_X) | 132 (1u << ADDR_SW_64KB_S_X) | 133 (1u << ADDR_SW_64KB_D_X) | 134 (1u << ADDR_SW_64KB_R_X) | 135 Gfx10BlkVarSwModeMask; 136 137 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask; 138 139 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask; 140 141 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 142 (1u << ADDR_SW_64KB_R_X); 143 144 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | 145 Gfx10BlkVarSwModeMask; 146 147 const UINT_32 Gfx10Rsrc3dViewAs2dSwModeMask = Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask; 148 149 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask); 150 151 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask; 152 153 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask; 154 155 const UINT_32 Gfx10MsaaSwModeMask = (Gfx10ZSwModeMask | 156 Gfx10RenderSwModeMask); 157 158 const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 159 (1u << ADDR_SW_4KB_S) | 160 (1u << ADDR_SW_64KB_S) | 161 (1u << ADDR_SW_64KB_S_T) | 162 (1u << ADDR_SW_4KB_S_X) | 163 (1u << ADDR_SW_64KB_S_X) | 164 (1u << ADDR_SW_64KB_R_X); 165 166 const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 167 (1u << ADDR_SW_64KB_D) | 168 (1u << ADDR_SW_64KB_D_T) | 169 (1u << ADDR_SW_4KB_D_X) | 170 (1u << ADDR_SW_64KB_D_X) | 171 Dcn20NonBpp64SwModeMask; 172 173 const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 174 (1u << ADDR_SW_64KB_S) | 175 (1u << ADDR_SW_64KB_S_T) | 176 (1u << ADDR_SW_64KB_S_X) | 177 (1u << ADDR_SW_64KB_R_X); 178 179 const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 180 (1u << ADDR_SW_64KB_D_T) | 181 (1u << ADDR_SW_64KB_D_X) | 182 Dcn21NonBpp64SwModeMask; 183 184 /** 185 ************************************************************************************************************************ 186 * @brief This class is the GFX10 specific address library 187 * function set. 188 ************************************************************************************************************************ 189 */ 190 class Gfx10Lib : public Lib 191 { 192 public: 193 /// Creates Gfx10Lib object CreateObj(const Client * pClient)194 static Addr::Lib* CreateObj(const Client* pClient) 195 { 196 VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient); 197 return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL; 198 } 199 200 protected: 201 Gfx10Lib(const Client* pClient); 202 virtual ~Gfx10Lib(); 203 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)204 virtual BOOL_32 HwlIsStandardSwizzle( 205 AddrResourceType resourceType, 206 AddrSwizzleMode swizzleMode) const 207 { 208 return m_swizzleModeTable[swizzleMode].isStd; 209 } 210 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)211 virtual BOOL_32 HwlIsDisplaySwizzle( 212 AddrResourceType resourceType, 213 AddrSwizzleMode swizzleMode) const 214 { 215 return m_swizzleModeTable[swizzleMode].isDisp; 216 } 217 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)218 virtual BOOL_32 HwlIsThin( 219 AddrResourceType resourceType, 220 AddrSwizzleMode swizzleMode) const 221 { 222 return ((IsTex1d(resourceType) == TRUE) || 223 (IsTex2d(resourceType) == TRUE) || 224 ((IsTex3d(resourceType) == TRUE) && 225 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 226 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 227 } 228 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)229 virtual BOOL_32 HwlIsThick( 230 AddrResourceType resourceType, 231 AddrSwizzleMode swizzleMode) const 232 { 233 return ((IsTex3d(resourceType) == TRUE) && 234 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 235 } 236 237 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 238 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 239 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 240 241 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 242 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 243 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 244 245 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 246 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 247 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 248 249 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 250 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 251 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 252 253 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 254 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 255 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 256 257 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 258 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 259 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 260 261 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 262 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 263 264 virtual VOID HwlComputeDccAddrFromCoord( 265 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 266 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 267 268 virtual UINT_32 HwlGetEquationIndex( 269 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 270 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 271 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)272 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 273 { 274 *ppEquationTable = m_equationTable; 275 276 return m_numEquations; 277 } 278 279 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 280 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 281 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 282 283 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 284 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 285 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 286 287 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 288 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 289 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 290 291 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 292 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 293 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const; 294 295 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 296 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 297 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 298 299 virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes( 300 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 301 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 302 303 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 304 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 305 306 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 307 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 308 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 309 310 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 311 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 312 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 313 314 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 315 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 316 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 317 318 virtual ADDR_E_RETURNCODE HwlCopyMemToSurface( 319 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 320 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 321 UINT_32 regionCount) const; 322 323 virtual ADDR_E_RETURNCODE HwlCopySurfaceToMem( 324 const ADDR2_COPY_MEMSURFACE_INPUT* pIn, 325 const ADDR2_COPY_MEMSURFACE_REGION* pRegions, 326 UINT_32 regionCount) const; 327 328 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 329 330 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 331 332 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 333 334 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 335 336 private: 337 // Initialize equation table 338 VOID InitEquationTable(); 339 340 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 341 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 342 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 343 344 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 345 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 346 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 347 348 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 349 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 350 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 351 352 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 353 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 354 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 355 356 UINT_32 ComputeOffsetFromEquation( 357 const ADDR_EQUATION* pEq, 358 UINT_32 x, 359 UINT_32 y, 360 UINT_32 z) const; 361 362 ADDR_E_RETURNCODE ComputeStereoInfo( 363 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 364 UINT_32* pAlignY, 365 UINT_32* pRightXor) const; 366 367 static void GetMipSize( 368 UINT_32 mip0Width, 369 UINT_32 mip0Height, 370 UINT_32 mip0Depth, 371 UINT_32 mipId, 372 UINT_32* pMipWidth, 373 UINT_32* pMipHeight, 374 UINT_32* pMipDepth = NULL) 375 { 376 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 377 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 378 379 if (pMipDepth != NULL) 380 { 381 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 382 } 383 } 384 385 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 386 AddrSwizzleMode swizzleMode, 387 AddrResourceType resourceType, 388 UINT_32 log2Elem, 389 UINT_32 numFrag) const; 390 391 /** 392 * Will use the indices, "nibbles", to build an index equation inside pSwizzle 393 * 394 * @param pPatInfo Pointer to a patInfo. Contains indices mapping to the 2D nibble arrays which will be used to build an index equation. 395 * @param pSwizzle Array to write the index equation to. 396 */ GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[ADDR_MAX_EQUATION_BIT])397 VOID GetSwizzlePatternFromPatternInfo( 398 const ADDR_SW_PATINFO* pPatInfo, 399 ADDR_BIT_SETTING (&pSwizzle)[ADDR_MAX_EQUATION_BIT]) const 400 { 401 memcpy(pSwizzle, 402 GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 403 sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 404 405 memcpy(&pSwizzle[8], 406 GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 407 sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 408 409 memcpy(&pSwizzle[12], 410 GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 411 sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 412 413 memcpy(&pSwizzle[16], 414 GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 415 sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 416 } 417 418 VOID ConvertSwizzlePatternToEquation( 419 UINT_32 elemLog2, 420 AddrResourceType rsrcType, 421 AddrSwizzleMode swMode, 422 const ADDR_SW_PATINFO* pPatInfo, 423 ADDR_EQUATION* pEquation) const; 424 425 static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType); 426 427 static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType); 428 429 void GetBlk256SizeLog2( 430 AddrResourceType resourceType, 431 AddrSwizzleMode swizzleMode, 432 UINT_32 elemLog2, 433 UINT_32 numSamplesLog2, 434 Dim3d* pBlock) const; 435 436 void GetCompressedBlockSizeLog2( 437 Gfx10DataType dataType, 438 AddrResourceType resourceType, 439 AddrSwizzleMode swizzleMode, 440 UINT_32 elemLog2, 441 UINT_32 numSamplesLog2, 442 Dim3d* pBlock) const; 443 444 INT_32 GetMetaOverlapLog2( 445 Gfx10DataType dataType, 446 AddrResourceType resourceType, 447 AddrSwizzleMode swizzleMode, 448 UINT_32 elemLog2, 449 UINT_32 numSamplesLog2) const; 450 451 INT_32 Get3DMetaOverlapLog2( 452 AddrResourceType resourceType, 453 AddrSwizzleMode swizzleMode, 454 UINT_32 elemLog2) const; 455 456 UINT_32 GetMetaBlkSize( 457 Gfx10DataType dataType, 458 AddrResourceType resourceType, 459 AddrSwizzleMode swizzleMode, 460 UINT_32 elemLog2, 461 UINT_32 numSamplesLog2, 462 BOOL_32 pipeAlign, 463 Dim3d* pBlock) const; 464 465 INT_32 GetPipeRotateAmount( 466 AddrResourceType resourceType, 467 AddrSwizzleMode swizzleMode) const; 468 GetEffectiveNumPipes()469 INT_32 GetEffectiveNumPipes() const 470 { 471 return ((m_settings.supportRbPlus == FALSE) || 472 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1; 473 } 474 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)475 BOOL_32 IsRbAligned( 476 AddrResourceType resourceType, 477 AddrSwizzleMode swizzleMode) const 478 { 479 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 480 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 481 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 482 483 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 484 (IsTex3d(resourceType) && isDisplay); 485 486 } 487 488 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 489 490 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 491 492 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 493 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)494 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 495 { 496 ADDR2_BLOCK_SET allowedBlockSet = {}; 497 498 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE; 499 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE; 500 allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE; 501 502 if (rsrcType == ADDR_RSRC_TEX_3D) 503 { 504 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 505 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 506 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 507 } 508 else 509 { 510 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE; 511 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE; 512 } 513 514 return allowedBlockSet; 515 } 516 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)517 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 518 { 519 ADDR2_SWTYPE_SET allowedSwSet = {}; 520 521 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE; 522 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE; 523 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE; 524 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE; 525 526 return allowedSwSet; 527 } 528 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)529 BOOL_32 IsInMipTail( 530 Dim3d mipTailDim, 531 UINT_32 maxNumMipsInTail, 532 UINT_32 mipWidth, 533 UINT_32 mipHeight, 534 UINT_32 numMipsToTheEnd) const 535 { 536 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 537 (mipHeight <= mipTailDim.h) && 538 (numMipsToTheEnd <= maxNumMipsInTail)); 539 540 return inTail; 541 } 542 GetBankXorBits(UINT_32 blockBits)543 UINT_32 GetBankXorBits(UINT_32 blockBits) const 544 { 545 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 546 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 547 } 548 549 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 550 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 551 552 static const UINT_32 ColumnBits = 2; 553 static const UINT_32 BankBits = 4; 554 static const UINT_32 UnalignedDccType = 3; 555 556 static const Dim3d Block256_3d[MaxNumOfBpp]; 557 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 558 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 559 560 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 561 562 // Number of packers log2 563 UINT_32 m_numPkrLog2; 564 // Number of shader array log2 565 UINT_32 m_numSaLog2; 566 567 Gfx10ChipSettings m_settings; 568 569 UINT_32 m_colorBaseIndex; 570 UINT_32 m_xmaskBaseIndex; 571 UINT_32 m_htileBaseIndex; 572 UINT_32 m_dccBaseIndex; 573 }; 574 575 } // V2 576 } // Addr 577 578 #endif 579 580