1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: HAL Layer Specifications. 15 * Create: 2022-2-17 16 */ 17 18 #ifndef __HAL_COMMON_OPS_DEVICE_H__ 19 #define __HAL_COMMON_OPS_DEVICE_H__ 20 21 /***************************************************************************** 22 1 头文件包含 23 *****************************************************************************/ 24 #include "wlan_types.h" 25 #include "oal_types_device_rom.h" 26 #include "hal_common_ops_device_rom.h" 27 28 #ifdef __cplusplus 29 #if __cplusplus 30 extern "C" { 31 #endif 32 #endif 33 34 #define HAL_POW_CUSTOM_24G_HE40_RATE_NUM 3 35 #define HAL_POW_CUSTOM_5G_HE20_RATE_NUM 3 36 #define HAL_POW_CUSTOM_5G_HE40_RATE_NUM 3 37 #define HAL_POW_CUSTOM_5G_HE80_RATE_NUM 3 38 39 #define NUM_OF_NV_TOTAL_MAX_TXPOWER 124 40 41 #define HAL_CUS_NUM_5G_BW 4 /* 定制化5g带宽数 */ 42 43 #define HAL_NUM_5G_160M_SIDE_BAND 2 44 45 #define HAL_POW_MAX_CHAIN_NUM 2 /* 最大通道数 */ 46 47 #define HAL_2G_POW_UPC_RF_LUT_NUM 256 /* UPC在RF中的档位数目 8bit */ 48 #define HAL_5G_POW_UPC_RF_LUT_NUM 64 49 50 #define HAL_POW_11B_LPF_BASE_IDX 1 /* 11B基准LPF Index */ 51 52 #define HAL_POW_5G_6P5MBPS_RATE_POW_IDX 12 /* 5G 6.5Mbps对应的功率表索引, ht20 mcs0 */ 53 54 55 /***************************************************************************** 56 3 枚举 57 *****************************************************************************/ 58 59 /* 2.4GHz频段: 信道号对应的信道索引值 */ 60 typedef enum { 61 HAL_2G_CHANNEL1 = 0, 62 HAL_2G_CHANNEL2 = 1, 63 HAL_2G_CHANNEL3 = 2, 64 HAL_2G_CHANNEL4 = 3, 65 HAL_2G_CHANNEL5 = 4, 66 HAL_2G_CHANNEL6 = 5, 67 HAL_2G_CHANNEL7 = 6, 68 HAL_2G_CHANNEL8 = 7, 69 HAL_2G_CHANNEL9 = 8, 70 HAL_2G_CHANNEL10 = 9, 71 HAL_2G_CHANNEL11 = 10, 72 HAL_2G_CHANNEL12 = 11, 73 HAL_2G_CHANNEL13 = 12, 74 HAL_2G_CHANNEL14 = 13, 75 76 HAL_CHANNEL_FREQ_2G_BUTT = 14 77 } hal_channel_freq_2g_enum; 78 typedef osal_u8 hal_channel_freq_2g_enum_uint8; 79 80 typedef enum { 81 HAL_OPER_MODE_NORMAL, 82 HAL_OPER_MODE_HUT, 83 84 HAL_OPER_MODE_BUTT 85 } hal_oper_mode_enum; 86 typedef osal_u8 hal_oper_mode_enum_uint8; 87 88 /* RF测试用，用于指示配置TX描述符字段 */ 89 typedef enum { 90 HAL_RF_TEST_DATA_RATE_ZERO, 91 HAL_RF_TEST_BAND_WIDTH, 92 HAL_RF_TEST_CHAN_CODE, 93 HAL_RF_TEST_POWER, 94 HAL_RF_TEST_BUTT 95 } hal_rf_test_sect_enum; 96 typedef osal_u8 hal_rf_test_sect_enum_uint8; 97 98 /* 0~3代表AC发送队列，4代表管理帧、控制帧发送队列 */ 99 #define HAL_TX_QUEUE_MGMT HAL_TX_QUEUE_HI 100 101 /* HAL模块需要抛出的WLAN_CRX事件子类型的定义 102 说明:该枚举需要和dmac_wlan_crx_event_sub_type_enum_uint8枚举一一对应 */ 103 typedef enum { 104 HAL_WLAN_CRX_EVENT_SUB_TYPE_RX, /* WLAN CRX 流程 */ 105 106 #ifdef _PRE_WLAN_FEATURE_FTM 107 HAL_EVENT_DMAC_MISC_FTM_ACK_COMPLETE, /* FTM ACK发送完成中断 */ 108 #endif 109 HAL_WLAN_CRX_EVENT_SUB_RPT_HE_ROM, 110 HAL_WLAN_CRX_EVENT_SUB_RPT_TRIG_PARA, /* 收到Trig帧中断 */ 111 HAL_WLAN_CRX_EVENT_SUB_TYPE_BUTT 112 } hal_wlan_crx_event_sub_type_enum; 113 typedef osal_u8 hal_wlan_crx_event_sub_type_enum_uint8; 114 115 typedef enum { 116 HAL_TX_COMP_SUB_TYPE_TX, 117 HAL_TX_COMP_SUB_TYPE_AL_TX, 118 HAL_TX_COMP_SUB_TYPE_BUTT 119 } hal_tx_comp_sub_type_enum; 120 typedef osal_u8 hal_tx_comp_sub_type_enum_uint8; 121 122 /* 功率模式 */ 123 typedef enum { 124 HAL_POW_MODE_MARGIN = 0, /* 有余量模式: 默认 */ 125 HAL_POW_MODE_NO_MARGIN = 1, /* 没有余量模式 */ 126 127 HAL_POW_MODE_BUTT 128 } hal_pow_mode_enum; 129 typedef osal_u8 hal_pow_mode_enum_uint8; 130 131 typedef enum { 132 HAL_LPM_SOC_BUS_GATING = 0, 133 HAL_LPM_SOC_PCIE_RD_BYPASS = 1, 134 HAL_LPM_SOC_MEM_PRECHARGE = 2, 135 HAL_LPM_SOC_PCIE_L0 = 3, 136 HAL_LPM_SOC_PCIE_L1_PM = 4, 137 HAL_LPM_SOC_AUTOCG_ALL = 5, 138 HAL_LPM_SOC_ADC_FREQ = 6, 139 HAL_LPM_SOC_PCIE_L1S = 7, 140 141 HAL_LPM_SOC_SET_BUTT 142 } hal_lpm_soc_set_enum; 143 typedef osal_u8 hal_lpm_soc_set_enum_uint8; 144 145 #ifdef _PRE_WLAN_FEATURE_SMPS 146 /* SMPS模式配置 147 00：SMPS_STATIC（始终单路接收） 148 01：SMPS_DYNAMIC 149 10：reserved 150 11：SMPS_DISABLE（始终多路接收） */ 151 typedef enum { 152 HAL_SMPS_MODE_STATIC = 0, 153 HAL_SMPS_MODE_DYNAMIC = 1, 154 HAL_SMPS_MODE_DISABLE = 3, 155 156 HAL_SMPS_MODE_BUTT 157 } hal_smps_mode_enum; 158 159 typedef osal_u8 hal_smps_mode_enum_uint8; 160 #endif 161 162 #ifdef _PRE_WLAN_FEATURE_DFS 163 typedef enum { 164 HAL_RADAR_NOT_REPORT = 0, 165 HAL_RADAR_REPORT, 166 } hal_radar_filter_enum; 167 typedef osal_u8 hal_radar_filter_enum_uint8; 168 #endif 169 170 /***************************************************************************** 171 STRUCT定义 172 *****************************************************************************/ 173 174 typedef struct { 175 /* PHY TX MODE 2 (第15行) */ 176 osal_u8 tx_rts_antenna; /* 发送RTS使用的天线组合 */ 177 osal_u8 rx_ctrl_antenna; /* 接收CTS/ACK/BA使用的天线组合 */ 178 osal_u8 reserve1[1]; /* TX VAP index 不是算法填写，故在此也填0 */ 179 180 /* 0代表允许TXOP POWER save，1代表不允许TXOP POWER save */ 181 osal_u8 txop_ps_not_allowed : 1; 182 183 /* NAV保护enable字段，1代表Long nav保护，0代表non long nav保护 */ 184 osal_u8 long_nav_enable : 1; 185 186 /* 这个字段暂时由软件填写，最终可能由算法填写，故先列出 */ 187 osal_u8 group_id : 6; 188 } hal_tx_txop_antenna_params_stru; 189 190 #define RADAR_INFO_FLAG_DUMMY 0x10 191 192 /* 脉冲信息结构体 */ 193 typedef struct { 194 osal_u32 timestamp; 195 osal_u16 duration; 196 osal_u16 power; 197 osal_u16 max_fft; 198 osal_u8 type; 199 osal_u8 auc_resv[1]; 200 } hal_pulse_info_stru; 201 202 #define MAX_RADAR_PULSE_NUM 32 /* 最大雷达脉冲数 */ 203 #define RADAR_TYPE_CHIRP 10 /* 芯片上报的chirp雷达类型标号 */ 204 #define RADAR_MIN_ETSI_CHIRP_PULSE_NUM 5 /* ETSI chirp最小脉冲个数 */ 205 206 /* 保存多个脉冲信息结构体 */ 207 typedef struct { 208 hal_pulse_info_stru pulse_info[MAX_RADAR_PULSE_NUM]; 209 osal_u32 pulse_cnt; 210 } hal_radar_pulse_info_stru; 211 212 /* 对DMAC SCAN模块提供的硬件雷达检测信息结构体 */ 213 typedef struct { 214 #ifdef _PRE_WLAN_FEATURE_DFS 215 hal_radar_pulse_info_stru radar_pulse_info; 216 #endif 217 osal_u8 radar_type; 218 osal_u8 radar_freq_offset; 219 osal_u8 radar_bw; 220 osal_u8 band; 221 osal_u8 channel_num; 222 osal_u8 working_bw; 223 osal_u8 flag; 224 osal_u8 resv; 225 } hal_radar_det_event_stru; 226 227 typedef struct { 228 osal_u32 reg_band_info; 229 osal_u32 reg_bw_info; 230 osal_u32 reg_ch_info; 231 } hal_radar_irq_reg_list_stru; 232 233 typedef enum { 234 HAL_WOW_PARA_EN = BIT0, 235 HAL_WOW_PARA_NULLDATA = BIT1, 236 HAL_WOW_PARA_NULLDATA_INTERVAL = BIT2, 237 HAL_WOW_PARA_NULLDATA_AWAKE = BIT3, 238 HAL_WOW_PARA_AP0_PROBE_RESP = BIT4, 239 HAL_WOW_PARA_AP1_PROBE_RESP = BIT5, 240 HAL_WOW_PARA_AP0_IS_FAKE_VAP = BIT6, 241 HAL_WOW_PARA_AP1_IS_FAKE_VAP = BIT7, 242 243 HAL_WOW_PARA_BUTT 244 } hal_wow_para_set_enum; 245 typedef osal_u32 hal_tx_status_enum_uint32; 246 247 248 #ifdef _PRE_WLAN_FEATURE_DFS 249 typedef struct { 250 /* 误报新增过滤条件 */ 251 osal_u8 fcc_chirp_duration_diff : 1; 252 osal_u8 fcc_chirp_pow_diff : 1; 253 osal_u8 fcc_type4_duration_diff : 1; 254 osal_u8 fcc_chirp_eq_duration_num : 1; 255 osal_u8 resv : 4; 256 } hal_dfs_pulse_check_filter_stru; 257 258 typedef struct { 259 /* normal pulse det */ 260 osal_u8 irq_cnt; 261 osal_u8 radar_cnt; 262 osal_u8 irq_cnt_old; 263 osal_u8 timeout : 1; 264 osal_u8 timer_start : 1; 265 osal_u8 is_enabled : 1; 266 osal_u8 resv : 5; 267 268 osal_u32 period_cnt; 269 frw_timeout_stru timer; 270 } hal_dfs_normal_pulse_det_stru; 271 272 typedef struct { 273 #ifdef _PRE_WLAN_FEATURE_DFS 274 osal_u8 chirp_enable : 1; 275 osal_u8 chirp_wow_wake_flag : 1; /* 在wow的gpio中断上半部标记，表示刚从wow唤醒 */ 276 osal_u8 log_switch : 2; 277 osal_u8 radar_type : 3; 278 osal_u8 chirp_timeout : 1; 279 280 osal_u8 chirp_cnt; 281 osal_u8 chirp_cnt_total; 282 osal_u8 chirp_cnt_for_crazy_report_det; 283 284 osal_u32 last_timestamp_for_chirp_pulse; 285 286 frw_timeout_stru timer; 287 osal_u32 min_pri; 288 289 /* 误报过滤条件 */ 290 hal_dfs_pulse_check_filter_stru dfs_pulse_check_filter; 291 292 /* crazy report det */ 293 osal_u8 crazy_report_cnt : 1; 294 osal_u8 crazy_report_is_enabled : 1; 295 osal_u8 resv0 : 6; 296 osal_u8 resv1[2]; /* 2byte保留字段 */ 297 298 frw_timeout_stru timer_crazy_report_det; 299 frw_timeout_stru timer_disable_chirp_det; 300 301 /* normal pulse det timer */ 302 hal_dfs_normal_pulse_det_stru dfs_normal_pulse_det; 303 304 #else 305 osal_u8 chirp_enable : 1; 306 osal_u8 chirp_wow_wake_flag : 1; /* 在wow的gpio中断上半部标记，表示刚从wow唤醒 */ 307 osal_u8 resv : 6; 308 osal_u8 resv0[3]; /* 3byte保留字段 */ 309 #endif 310 osal_u32 chirp_time_threshold; 311 osal_u32 chirp_cnt_threshold; 312 osal_u32 time_threshold; 313 osal_u32 last_burst_timestamp; 314 osal_u32 last_burst_timestamp_for_chirp; 315 } hal_dfs_radar_filter_stru; 316 #endif 317 318 typedef struct { 319 osal_u32 rx_rate; 320 osal_u16 rx_rate_stat_count; 321 oal_bool_enum_uint8 compatibility_enable; 322 oal_bool_enum_uint8 compatibility_stat; 323 osal_u32 compatibility_rate_limit[WLAN_BW_CAP_BUTT][WLAN_PROTOCOL_BUTT]; 324 } hal_compatibility_stat_stru; 325 326 typedef struct { 327 osal_u32 *cnt1; 328 osal_u32 *cnt2; 329 osal_u32 *cnt3; 330 osal_u32 *cnt4; 331 osal_u32 *cnt5; 332 osal_u32 *cnt6; 333 } machw_rx_err_count_stru; 334 335 typedef struct { 336 osal_u8 cali_gear; 337 osal_u8 cali_data; 338 osal_s8 cali_offset; 339 osal_u8 ant; 340 osal_u8 pga_unit_deta_one; 341 osal_u8 pga_unit_deta_two; 342 } hal_pow_tpc_cali_stru; 343 344 #ifdef __cplusplus 345 #if __cplusplus 346 } 347 #endif 348 #endif 349 350 #endif 351