1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 * Description: Header file of HAL external public interfaces .
15 */
16
17 #ifndef HAL_EXT_IF_ROM_H
18 #define HAL_EXT_IF_ROM_H
19
20 /*****************************************************************************
21 1 其他头文件包含
22 *****************************************************************************/
23 #include "oal_ext_if_rom.h"
24 #include "oam_ext_if.h"
25 #include "frw_ext_if_rom.h"
26 #include "wlan_types_rom.h"
27 #include "hal_common_ops_rom.h"
28 #include "hal_ext_if_device_rom.h"
29 #ifdef _PRE_WLAN_FEATURE_AMPDU
30 #include "hal_ampdu_rom.h"
31 #endif
32 #include "hal_power_save_rom.h"
33 #ifdef _PRE_WLAN_FEATURE_INTF_DET
34 #include "hal_ext_intf_det_rom.h"
35 #endif
36
37 #ifdef __cplusplus
38 #if __cplusplus
39 extern "C" {
40 #endif
41 #endif
42 #undef THIS_FILE_ID
43 #define THIS_FILE_ID OAM_FILE_ID_HAL_EXT_IF_ROM_H
44
hal_reg_read16(osal_u32 addr)45 static INLINE__ osal_u16 hal_reg_read16(osal_u32 addr)
46 {
47 return *(volatile osal_u16 *)(uintptr_t)addr;
48 }
49
hal_reg_write16(osal_u32 addr,osal_u16 val)50 static INLINE__ osal_void hal_reg_write16(osal_u32 addr, osal_u16 val)
51 {
52 *((volatile osal_u16 *)(uintptr_t)addr) = (val);
53 }
54
hal_reg_read(osal_u32 addr)55 static INLINE__ osal_u32 hal_reg_read(osal_u32 addr)
56 {
57 return *(volatile osal_u32 *)(uintptr_t)addr;
58 }
59
hal_reg_write(osal_u32 addr,osal_u32 val)60 static INLINE__ osal_void hal_reg_write(osal_u32 addr, osal_u32 val)
61 {
62 *((volatile osal_u32 *)(uintptr_t)addr) = (val);
63 }
64
hal_reg_read_bit(osal_u32 addr,osal_u8 offset,osal_u8 bits)65 static INLINE__ osal_u32 hal_reg_read_bit(osal_u32 addr, osal_u8 offset, osal_u8 bits)
66 {
67 osal_u32 value = hal_reg_read(addr);
68
69 return (value >> offset) & (((osal_u32)1 << bits) - 1);
70 }
71
hal_reg_write_bits(osal_u32 reg_addr,osal_u8 offset,osal_u8 bits,osal_u32 reg_val)72 static INLINE__ osal_void hal_reg_write_bits(osal_u32 reg_addr, osal_u8 offset, osal_u8 bits, osal_u32 reg_val)
73 {
74 osal_u32 value = hal_reg_read(reg_addr);
75 value &= ~((((osal_u32)1 << bits) - 1) << offset); /* 先将对应bits位的值清0 */
76 value |= ((reg_val & (((osal_u32)1 << bits) - 1)) << offset); /* 将对应bits值改写为配置值 */
77 hal_reg_write(reg_addr, value);
78 }
79
80 /*****************************************************************************
81 功能描述 : 写表寄存器的值
82 *****************************************************************************/
hal_reg_read_tbl(hal_reg32_cfg_stru * reg_tbl,osal_u8 tbl_len)83 static INLINE__ osal_void hal_reg_read_tbl(hal_reg32_cfg_stru *reg_tbl, osal_u8 tbl_len)
84 {
85 osal_u8 index;
86 for (index = 0; index < tbl_len; index++) {
87 reg_tbl[index].value = hal_reg_read(reg_tbl[index].address);
88 }
89 }
90
91 /*****************************************************************************
92 功能描述 : 读取表寄存器的值
93 *****************************************************************************/
hal_reg_write_tbl(const hal_reg32_cfg_stru * reg_tbl,osal_u8 tbl_len)94 static INLINE__ osal_void hal_reg_write_tbl(const hal_reg32_cfg_stru *reg_tbl, osal_u8 tbl_len)
95 {
96 osal_u8 index;
97 for (index = 0; index < tbl_len; index++) {
98 hal_reg_write(reg_tbl[index].address, reg_tbl[index].value);
99 }
100 }
101
hal_reg_write16_tbl(const hal_reg16_cfg_stru * reg_tbl,osal_u8 tbl_len)102 static INLINE__ osal_void hal_reg_write16_tbl(const hal_reg16_cfg_stru *reg_tbl, osal_u8 tbl_len)
103 {
104 osal_u8 index;
105 for (index = 0; index < tbl_len; index++) {
106 hal_reg_write16(reg_tbl[index].address, reg_tbl[index].value);
107 }
108 }
109
110 hal_cfg_cap_info_stru *hal_device_get_cfg_custom_addr(osal_void);
111 osal_void hal_rf_cali_set_calidata_mask(const osal_u8 *param);
112
113 // mac_err
114 typedef struct {
115 osal_void (* func)(hal_to_dmac_device_stru *hal_device, osal_u32 para);
116 osal_u32 param;
117 } hal_error_proc_stru;
118
119 hal_error_proc_stru get_err_proc_func(osal_u8 error_id);
120
121 osal_void hal_device_process_mac_error_status(osal_u32 error1_irq_state, osal_u32 error2_irq_state);
122
123 osal_void hal_mac_error_msg_report(hal_to_dmac_device_stru *hal_device, hal_mac_error_type_enum_uint8 error_type);
124
125 // vap tbtt bcn common user
126 osal_s32 hal_main_init(osal_void);
127
128 osal_void hal_main_exit(osal_void);
129
130 osal_void hal_add_vap(hal_to_dmac_device_stru *hal_device_base,
131 wlan_vap_mode_enum_uint8 vap_mode, osal_u8 hal_vap_id, hal_to_dmac_vap_stru **hal_vap);
132
133 osal_void hal_get_hal_vap(const hal_to_dmac_device_stru *hal_device_base, osal_u8 vap_id,
134 hal_to_dmac_vap_stru **hal_vap);
135
136 osal_void hal_del_vap(hal_to_dmac_device_stru *hal_device, osal_u8 vap_id);
137
138 osal_u8 hal_device_find_all_up_vap(const hal_to_dmac_device_stru *hal_device, osal_u8 *vap_id, osal_u8 lenth);
139 hal_to_dmac_device_stru *hal_chip_get_hal_device(osal_void);
140
141 osal_void hal_vap_beacon_suspend(const hal_to_dmac_vap_stru *hal_vap);
142
143 osal_void hal_vap_beacon_resume(const hal_to_dmac_vap_stru *hal_vap);
144
145 osal_void hal_vap_send_beacon_pkt(const hal_to_dmac_vap_stru *hal_vap, const hal_beacon_tx_params_stru *params);
146
147 osal_void hal_vap_set_machw_beacon_period(const hal_to_dmac_vap_stru *hal_vap, osal_u16 beacon_period);
148
149 osal_void hal_register_alg_isr_hook(struct tag_hal_to_dmac_device_stru *hal_to_dmac_device,
150 hal_isr_type_enum_uint8 isr_type, hal_alg_noify_enum_uint8 alg_notify, p_hal_alg_isr_func func);
151
152 osal_void hal_vap_tsf_get_32bit(const hal_to_dmac_vap_stru *hal_vap, osal_u32 *tsf_lo);
153
154 osal_void hal_enable_tsf_tbtt(hal_to_dmac_vap_stru *hal_vap, oal_bool_enum_uint8 dbac_enable);
155
156 osal_void hal_vap_read_tbtt_timer(const hal_to_dmac_vap_stru *hal_vap, osal_u32 *value);
157
158 osal_void hal_vap_get_beacon_period(const hal_to_dmac_vap_stru *hal_vap, osal_u32 *beacon_period);
159
160 osal_void hal_vap_tsf_get_64bit(const hal_to_dmac_vap_stru *hal_vap, osal_u32 *tsf_high, osal_u32 *tsf_lo);
161
162 osal_void hal_vap_write_tbtt_timer(const hal_to_dmac_vap_stru *hal_vap, osal_u32 value);
163 osal_void hal_vap_tsf_set_64bit(const hal_to_dmac_vap_stru *hal_vap, osal_u32 tsf_hi, osal_u32 tsf_lo);
164
get_hal_dev_current_scan_idx(hal_to_dmac_device_stru * hal_device)165 static INLINE__ osal_u8 get_hal_dev_current_scan_idx(hal_to_dmac_device_stru *hal_device)
166 {
167 return hal_device->hal_scan_params.start_chan_idx + hal_device->hal_scan_params.scan_chan_idx;
168 }
169
170 osal_u8 hal_dev_fsm_get_curr_state(osal_void);
171
hal_device_state_is_busy(osal_void)172 static INLINE__ osal_bool hal_device_state_is_busy(osal_void)
173 {
174 return (hal_dev_fsm_get_curr_state() == HAL_DEVICE_WORK_STATE) ||
175 (hal_dev_fsm_get_curr_state() == HAL_DEVICE_SCAN_STATE) ? OSAL_TRUE : OSAL_FALSE;
176 }
177 osal_void hal_device_inc_assoc_user_nums(hal_to_dmac_device_stru *hal_device);
178 osal_void hal_device_dec_assoc_user_nums(hal_to_dmac_device_stru *hal_device);
179 // power tpc
180 osal_void hal_pow_get_spec_frame_data_rate_idx(osal_u8 rate, osal_u8 *rate_idx);
181 osal_u16 hal_pow_get_pow_table_tpc_code(osal_u8 band, osal_u8 rate, osal_u8 bw, osal_u8 pwr_lvl);
182 osal_u16 hal_pow_get_pow_table_tpc_code_for_dscr(osal_u8 band, osal_u8 mcs, osal_u8 protocol_mode, osal_u8 bw,
183 osal_u8 pwr_lvl);
184 // forward
185 osal_void hal_gp_set_mpdu_count(osal_u32 netbuf_reserve, osal_u32 large_free, osal_u32 short_free, osal_u32 mgmt_free);
186 osal_void hal_clear_tx_hw_queue(hal_to_dmac_device_stru *hal_device);
187 osal_void hal_clear_hw_fifo(hal_to_dmac_device_stru *hal_device);
188 oal_bool_enum_uint8 hal_is_hw_tx_queue_empty(hal_to_dmac_device_stru *hal_device);
189 osal_void hal_flush_tx_complete_irq(hal_to_dmac_device_stru *hal_dev);
190 osal_void hal_flush_rx_queue_complete_irq(hal_to_dmac_device_stru *hal_dev, hal_rx_dscr_queue_id_enum_uint8 queue_num);
191
192 // one pkt
193 osal_void hal_get_one_packet_status(hal_one_packet_debug_stru *status);
194 osal_void hal_one_packet_start(hal_to_dmac_device_stru *hal_device,
195 const hal_one_packet_cfg_stru *cfg);
196 osal_void hal_one_packet_stop(hal_to_dmac_device_stru *hal_device);
197 osal_void hal_send_one_packet(hal_to_dmac_device_stru *device, hal_one_packet_cfg_stru *one_packet_cfg,
198 hal_one_packet_status_stru *status, osal_u16 wait_timeout);
199
200 // dbac
201 osal_u32 hal_gp_get_dbac_vap_stop_bitmap(osal_void);
202 osal_void hal_gp_set_dbac_vap_stop_bitmap(osal_u32 val);
203
204 osal_void hal_disable_machw_phy_and_pa(osal_void);
205 osal_void hal_enable_machw_phy_and_pa(const hal_to_dmac_device_stru *hal_device);
206 osal_void hal_recover_machw_phy_and_pa(hal_to_dmac_device_stru *hal_device);
207
208 // slp
209 osal_void hal_gp_set_slp_tx_ctrl(osal_u32 val);
210 osal_u32 hal_gp_get_slp_tx_ctrl(osal_void);
211
212 // protocol
213 osal_void hal_get_bcn_rate(const hal_to_dmac_vap_stru *hal_vap, osal_u8 *data_rate);
214
215 osal_void hal_reset_nav_timer(osal_void);
216
217 osal_void hal_device_get_fix_rate_pow_code_idx(const hal_tx_ctrl_desc_rate_stru *rate_param,
218 osal_u8 *rate_pow_idx);
219
220 // channel mgmt
221 osal_void hal_set_freq_band(hal_to_dmac_device_stru *hal_device, wlan_channel_band_enum_uint8 band);
222 osal_void hal_set_bandwidth_mode(hal_to_dmac_device_stru *hal_device,
223 wlan_channel_bandwidth_enum_uint8 bandwidth);
224 osal_void hal_set_primary_channel(hal_to_dmac_device_stru *hal_device, osal_u8 channel_num,
225 wlan_channel_band_enum_uint8 band, osal_u8 channel_idx, wlan_channel_bandwidth_enum_uint8 bandwidth);
226
227 osal_void hal_chan_measure_start(hal_chan_measure_stru *meas);
228
229 osal_void hal_get_ch_statics_result(hal_ch_statics_irq_event_stru *ch_statics);
230
231 // csi
232 osal_void hal_csi_set_sw_buff_index(osal_u8 cur_index);
233 osal_void hal_csi_set_data_base_addr(uintptr_t base_addr);
234 osal_void hal_csi_set_buff_step(osal_u16 buff_step);
235 osal_void hal_csi_set_buff_num(osal_u8 buff_num);
236
237 // pm
238 #ifdef _PRE_PM_TBTT_OFFSET_PROBE
239 osal_void hal_tbtt_offset_probe_destroy(hal_to_dmac_vap_stru *hal_vap);
240 osal_void hal_tbtt_offset_probe_tbtt_cnt_incr(hal_to_dmac_vap_stru *hal_vap);
241 osal_void hal_tbtt_offset_probe_beacon_cnt_incr(hal_to_dmac_vap_stru *hal_vap);
242 #endif
243 osal_void hal_pm_vote2platform(hal_pm_mode_enum_uint8 pm_mode);
244
245 osal_void hal_pm_servid_unregister(osal_void);
246
247 osal_void hal_pm_servid_register(osal_void);
248
249 #define HAL_PM_DEF_TBTT_OFFSET 10000 /* tbtt提前量默认值单位us */
250 #define HAL_PM_DEF_EXT_TSF_OFFSET 12500 /* 外置tsf唤醒提前量单位us */
251
252 // dscr
253 osal_void hal_tx_get_dscr_status(const hal_tx_dscr_stru *tx_dscr, osal_u8 *status);
254
255 osal_void hal_tx_get_dscr_send_rate_rank(const hal_tx_dscr_stru *tx_dscr, osal_u8 *send_rate_rank);
256
257 osal_void hal_tx_get_vap_id(const hal_to_dmac_device_stru *hal_device,
258 const hal_tx_dscr_stru *tx_dscr, osal_u8 *vap_id);
259
260 osal_void hal_tx_fill_basic_ctrl_dscr(const hal_to_dmac_device_stru *hal_device,
261 hal_tx_dscr_stru *tx_dscr, hal_tx_mpdu_stru *mpdu);
262
263 osal_void hal_tx_seqnum_set_dscr(hal_tx_dscr_stru *tx_dscr, osal_u16 seq_num);
264
265 osal_void hal_tx_get_dscr_seq_num(hal_tx_dscr_stru *tx_dscr, osal_u16 *seq_num);
266
267 osal_void hal_tx_ucast_data_set_dscr(hal_to_dmac_device_stru *device, hal_tx_dscr_stru *tx_dscr,
268 hal_tx_txop_alg_stru *txop_alg);
269
270 osal_void hal_tx_csi_set_rts_dscr(hal_tx_dscr_stru *tx_dscr);
271
272 osal_void hal_tx_set_dscr_status(hal_tx_dscr_stru *tx_dscr, osal_u8 status);
273
274 osal_void hal_rx_get_dscr_status(osal_u32 *rx_dscr, osal_u8 *dscr_status);
275
276 osal_void hal_rx_free_dscr_list(hal_to_dmac_device_stru *hal_device,
277 hal_rx_dscr_queue_id_enum_uint8 queue_num, osal_u32 *rx_dscr);
278
279 osal_void hal_rx_get_netbuffer_addr_dscr(osal_u32 *rx_dscr, oal_dmac_netbuf_stru **rx_next_amsdu_dscr);
280
281 osal_void hal_rx_init_dscr_queue(hal_to_dmac_device_stru *device, osal_u8 set_hw);
282
283 osal_void hal_rx_destroy_dscr_queue(hal_to_dmac_device_stru *device);
284
285 osal_void hal_al_rx_destroy_dscr_queue(hal_to_dmac_device_stru *hal_device);
286
287 osal_void hal_al_rx_init_dscr_queue(hal_to_dmac_device_stru *hal_device, osal_u16 size);
288
289 osal_void hal_tx_set_dscr_ba_ssn(hal_tx_dscr_stru *tx_dscr, osal_u16 ba_ssn);
290
291 osal_void hal_tx_set_dscr_ba_bitmap(hal_tx_dscr_stru *tx_dscr, osal_u32 word0, osal_u32 word1);
292
293 // wow to be removed
294 osal_void hal_ce_get_key(const hal_security_key_stru *security_key);
295 osal_void hal_ce_add_key(hal_security_key_stru *security_key);
296 osal_void hal_vap_get_gtk_rx_lut_idx(const hal_to_dmac_vap_stru *hal_vap, osal_u8 *lut_idx);
297 osal_void hal_gp_set_sdp_chnl_switch_off(osal_u32 val);
298 osal_void hal_gp_clear_dbac_vap_stop_bitmap(osal_void);
299 hal_cipher_protocol_type_enum_uint8 hal_cipher_suite_to_ctype(wlan_ciper_protocol_type_enum_uint8 cipher_suite);
300 wlan_ciper_protocol_type_enum_uint8 hal_ctype_to_cipher_suite(hal_cipher_protocol_type_enum_uint8 cipher_type);
301
302 osal_void hal_set_rf_limit_power(wlan_channel_band_enum_uint8 band, osal_u8 power);
303
304 osal_void hal_pow_set_user_resp_frame_tx_power(hal_to_dmac_device_stru *hal_device, osal_u8 lut_index,
305 osal_u8 rssi_distance);
306 osal_void hal_pow_set_band_spec_frame_tx_power(hal_to_dmac_device_stru *hal_device,
307 wlan_channel_band_enum_uint8 band, osal_u8 chan_idx);
308
309 osal_void hal_set_bcn_phy_tx_mode(const hal_to_dmac_vap_stru *hal_vap, osal_u32 pow_code);
310
311 osal_void hal_pow_set_four_rate_tx_dscr_power(hal_tx_txop_alg_stru *txop_param, const osal_u8 *pow_level,
312 hal_tx_txop_tpc_stru *tpc);
313
314 osal_void hal_pow_get_data_rate_idx(osal_u8 protocol_mode, osal_u8 mcs, wlan_bw_cap_enum_uint8 bw,
315 osal_u8 *rate_idx);
316
hal_m2s_check_btcoex_on(const hal_to_dmac_device_stru * hal_device)317 static INLINE__ osal_bool hal_m2s_check_btcoex_on(const hal_to_dmac_device_stru *hal_device)
318 {
319 osal_u8 tmp = *(osal_u8 *)&(hal_device->hal_m2s_fsm.m2s_mode);
320 if ((tmp & WLAN_M2S_TRIGGER_MODE_BTCOEX) != 0) {
321 return OSAL_TRUE;
322 } else {
323 return OSAL_FALSE;
324 }
325 }
326
get_hal_m2s_mode_tpye(const hal_to_dmac_device_stru * hal_device)327 static INLINE__ osal_u8 get_hal_m2s_mode_tpye(const hal_to_dmac_device_stru *hal_device)
328 {
329 return (*(osal_u8 *)&(hal_device->hal_m2s_fsm.m2s_mode));
330 }
331
hal_m2s_check_rssi_on(const hal_to_dmac_device_stru * hal_device)332 static INLINE__ osal_bool hal_m2s_check_rssi_on(const hal_to_dmac_device_stru *hal_device)
333 {
334 osal_u8 tmp = *(osal_u8 *)&(hal_device->hal_m2s_fsm.m2s_mode);
335 if ((tmp & WLAN_M2S_TRIGGER_MODE_RSSI) != 0) {
336 return OSAL_TRUE;
337 } else {
338 return OSAL_FALSE;
339 }
340 }
341
hal_m2s_check_command_on(const hal_to_dmac_device_stru * hal_device)342 static INLINE__ osal_bool hal_m2s_check_command_on(const hal_to_dmac_device_stru *hal_device)
343 {
344 osal_u8 tmp = *(osal_u8 *)&(hal_device->hal_m2s_fsm.m2s_mode);
345 if ((tmp & WLAN_M2S_TRIGGER_MODE_COMMAND) != 0) {
346 return OSAL_TRUE;
347 } else {
348 return OSAL_FALSE;
349 }
350 }
351
352 osal_void hal_pow_set_pow_code_idx_in_tpc(hal_tx_txop_tpc_stru *tpc,
353 const osal_u32 *tpc_code, osal_u16 tpc_code_size);
354
355 osal_u8 hal_pow_get_legacy_rate(hal_tx_ctrl_desc_rate_stru *tx_dscr);
356
357 osal_void hal_device_set_pow_al_tx(const hal_to_dmac_device_stru *hal_device,
358 osal_u8 band, hal_tx_txop_alg_stru *txop_alg);
359
360 osal_u32 hal_device_find_one_up_vap(hal_to_dmac_device_stru *hal_device, osal_u8 *mac_vap_id);
361 osal_u32 hal_device_find_another_up_vap(hal_to_dmac_device_stru *hal_device,
362 osal_u8 vap_id_self, osal_u8 *mac_vap_id);
363
364 /********** for ws63 **********/
365 #define HAL_ANT_SWITCH_RSSI_MGMT_ENABLE BIT0
366 #define HAL_ANT_SWITCH_RSSI_DATA_ENABLE BIT1
367
368 /********** for uranus **********/
369 osal_void hal_tx_dscr_get_rate(const hal_tx_dscr_stru *tx_dscr, osal_u8 rate_index, hal_tx_dscr_rate_stru *tx_rate);
370 osal_void hal_tx_dscr_get_protocol_mode(const hal_tx_dscr_stru *tx_dscr, osal_u8 rate_index, osal_u8 *protocol_mode);
371 /********** for uranus **********/
372 /*****************************************************************************
373 功能描述 : 释放保存mac寄存器的netbuf
374 *****************************************************************************/
375 osal_void hal_reset_free_reg_save(osal_void);
376 /*****************************************************************************
377 功能描述 : mac寄存器恢复
378 *****************************************************************************/
379 osal_void hal_reset_restore_mac_reg(osal_void);
380
381 /*****************************************************************************
382 功能描述 : MAC和PHY寄存器DMA方式恢复
383 *****************************************************************************/
384 osal_void hal_reset_dma_restore_reg(osal_void);
385 /*****************************************************************************
386 函 数 名 : hal_pm_enable_front_end
387 功能描述 : 低功耗唤醒前端操作
388 *****************************************************************************/
389 osal_void hal_pm_enable_front_end(hal_to_dmac_device_stru *hal_device, osal_u8 enable_paldo);
390 /*****************************************************************************
391 功能描述 : chip级别中断初始化(bt coex中断)
392 *****************************************************************************/
393 osal_void hal_chip_irq_init(osal_void);
394 hal_to_dmac_device_stru *hal_get_hal_to_dmac_device(osal_void);
395 osal_u32 hal_device_find_one_up_hal_vap(hal_to_dmac_device_stru *hal_device, osal_u8 *vap_id);
396 /*****************************************************************************
397 功能描述 : chip级别中断去初始化(bt coex中断)
398 *****************************************************************************/
399 osal_void hal_irq_init(osal_void);
400 osal_void hal_chip_irq_exit(osal_void);
401 osal_void hal_irq_exit(osal_void);
402 /*****************************************************************************
403 功能描述 : 屏蔽指定中断
404 *****************************************************************************/
405 osal_void hal_mask_interrupt(osal_u32 offset);
406 osal_void hal_pm_set_bcn_rf_chain(hal_to_dmac_vap_stru *hal_vap, osal_u8 bcn_rf_chain);
407
408 /*****************************************************************************
409 函 数 名 : hal_vap_get_machw_txop_limit_vivo
410 功能描述 : 获取VI、VO的TXOP上限(单位: 微秒)
411 *****************************************************************************/
hal_vap_get_machw_txop_limit_ac(osal_u8 ac,osal_u16 * txop)412 static INLINE__ osal_void hal_vap_get_machw_txop_limit_ac(osal_u8 ac, osal_u16 *txop)
413 {
414 hal_public_hook_func(_vap_get_machw_txop_limit_ac)(ac, txop);
415 }
416 #ifdef __cplusplus
417 #if __cplusplus
418 }
419 #endif
420 #endif
421
422 #endif /* end of hal_ext_if_rom.h */
423