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1 /*
2  * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  * Description: Header file for hal_mfg.c
15  */
16 
17 #ifndef HAL_MFG_H
18 #define HAL_MFG_H
19 #ifdef _PRE_WLAN_SUPPORT_CCPRIV_CMD
20 #ifdef _PRE_WLAN_FEATURE_MFG_TEST
21 /*****************************************************************************
22   1 头文件包含
23 *****************************************************************************/
24 #include "hal_ext_if.h"
25 #include "mac_vap_ext.h"
26 
27 #ifdef __cplusplus
28 #if __cplusplus
29 extern "C" {
30 #endif
31 #endif
32 
33 #define XO_TRIM_FINE ((osal_u32)(1 << 6))
34 #define XO_TRIM_COARSE ((osal_u32)(1 << 3))
35 #define XO_TRIM_ENABLE 1
36 #define MFG_MODE_ENABLE 1
37 #define XO_TRIM_DISABLE 0
38 #define CMD_MAX_LEN 256
39 #define WLAN_CFG_CON_OFFSET_NUM 2
40 #define WLAN_CFG_CMU_XO_TRIM_NUM 2
41 #define WLAN_CFG_MAC_GROUP_NUM 4
42 #define WLAN_CFG_POWER_INFO_NUM 7
43 #define RSSI_OFFSET_SIZE 3
44 #define WLAN_CFG_TEMPER_GEARS_STEP 10
45 #define EXT_EFUSE_CURVE_FACTOR_MAX 15
46 #define EFUSE_GROUP_MAX 3
47 #define EXT_EFUSE_IDX_GROUP 48
48 #define EFUSE_NAME_LEN 16
49 #define EFUSE_MAX_LEN 24
50 #define EXT_EFUSE_LOCK_MAX 255
51 #define SIZE_2_BITS 2
52 #define SIZE_3_BITS 3
53 #define SIZE_4_BITS 4
54 #define SIZE_8_BITS 8
55 #define SIZE_5_BITS 5
56 #define EXT_EFUSE_LOCK_XO_TRIM_BIT_POS 7
57 #define EXT_EFUSE_LOCK_POWER_BIT_POS 0
58 #define EXT_EFUSE_LOCK_RSSI_BIT_POS 1
59 #define EXT_EFUSE_LOCK_TEMP_BIT_POS 6
60 #define EXT_EFUSE_MFG_FLAG_BIT_POS 7
61 #define WLAN_CFG_ONE_POWER_PARAM_NUM 8
62 #define WLAN_CFG_COARSE_MIN_NUM 0
63 #define WLAN_CFG_COARSE_MAX_NUM 15
64 #define WLAN_CFG_FINE_MIN_NUM 0
65 #define WLAN_CFG_FINE_MAX_NUM 127
66 
67 typedef enum {
68     EXT_EFUSE_XO_TRIM_1_ID = 144,
69     EXT_EFUSE_XO_TRIM_COARSE_1_ID = 145,
70     EXT_EFUSE_CURV_FACTOR_LOW_1_ID = 146,
71     EXT_EFUSE_11B_HIGN_1_ID = 147,
72     EXT_EFUSE_11B_LOW_1_ID = 149,
73     EXT_EFUSE_OFDM_20M_HIGN_1_ID = 151,
74     EXT_EFUSE_OFDM_20M_LOW_1_ID = 153,
75     EXT_EFUSE_OFDM_40M_HIGN_1_ID = 153,
76     EXT_EFUSE_OFDM_40M_LOW_1_ID = 153,
77     EXT_EFUSE_RSSI_BAND1_1_ID = 159,
78     EXT_EFUSE_RSSI_BAND3_1_ID = 160,
79     EXT_EFUSE_TEMPERATURE_1_ID = 161,
80     EXT_EFUSE_XO_TRIM_2_ID = 162,
81     EXT_EFUSE_XO_TRIM_COARSE_2_ID = 163,
82     EXT_EFUSE_CURV_FACTOR_LOW_2_ID = 164,
83     EXT_EFUSE_11B_HIGN_2_ID = 165,
84     EXT_EFUSE_11B_LOW_2_ID = 167,
85     EXT_EFUSE_OFDM_20M_HIGN_2_ID = 169,
86     EXT_EFUSE_OFDM_20M_LOW_2_ID = 171,
87     EXT_EFUSE_OFDM_40M_HIGN_2_ID = 173,
88     EXT_EFUSE_OFDM_40M_LOW_2_ID = 175,
89     EXT_EFUSE_RSSI_BAND1_2_ID = 177,
90     EXT_EFUSE_RSSI_BAND3_2_ID = 178,
91     EXT_EFUSE_TEMPERATURE_2_ID = 179,
92     EXT_EFUSE_XO_TRIM_3_ID = 180,
93     EXT_EFUSE_XO_TRIM_COARSE_3_ID = 181,
94     EXT_EFUSE_CURV_FACTOR_LOW_3_ID = 182,
95     EXT_EFUSE_11B_HIGN_3_ID = 183,
96     EXT_EFUSE_11B_LOW_3_ID = 185,
97     EXT_EFUSE_OFDM_20M_HIGN_3_ID = 187,
98     EXT_EFUSE_OFDM_20M_LOW_3_ID = 189,
99     EXT_EFUSE_OFDM_40M_HIGN_3_ID = 191,
100     EXT_EFUSE_OFDM_40M_LOW_3_ID = 193,
101     EXT_EFUSE_RSSI_BAND1_3_ID = 195,
102     EXT_EFUSE_RSSI_BAND3_3_ID = 196,
103     EXT_EFUSE_TEMPERATURE_3_ID = 197,
104     EXT_EFUSE_IPV4_MAC_ADDR_01_ID = 198,
105     EXT_EFUSE_IPV4_MAC_ADDR_02_ID = 204,
106     EXT_EFUSE_IPV4_MAC_ADDR_03_ID = 210,
107     EXT_EFUSE_IPV4_MAC_ADDR_04_ID = 216,
108     EXT_EFUSE_MAX = 255,
109 } efuse_id;
110 
111 typedef enum {
112     EFUSE_OP_READ,               /* efuse读操作 */
113     EFUSE_OP_WRITE,              /* efuse写操作 */
114     EFUSE_OP_REMAIN,             /* efuse查询可用组数 */
115     EFUSE_OP_READ_ALL_MFG_DATA   /* 读取efuse所有校准数据 */
116 } efuse_op;
117 
118 typedef struct {
119     osal_char efuse_name[EFUSE_NAME_LEN]; /* efuse功能名 */
120     osal_u32 len;                         /* 数据长度 */
121     osal_u8 val[CMD_MAX_LEN];             /* 操作数据 */
122     osal_u8 op;                           /* 操作类型 */
123     osal_u8 resv[3];                      /* 保留3字节,4字节对齐 */
124 } efuse_operate_stru;
125 
126 typedef struct {
127     osal_u8 *data;
128     osal_u8 len;
129 } efuse_mfg_data_status;
130 
131 typedef struct {
132     osal_u8 curve_factor_hig;
133     osal_u8 curve_factor_low;
134     osal_u16 band1_hign;
135     osal_u16 band1_low;
136     osal_u16 ofdm_20m_hign;
137     osal_u16 ofdm_20m_low;
138     osal_u16 ofdm_40m_hign;
139     osal_u16 ofdm_40m_low;
140     osal_u8 resv[2];
141 } efuse_power_offset_stru;
142 
143 typedef struct {
144     osal_u16 xo_trim;                        /* 产测频偏校正码值 */
145     osal_u8 resv[2];
146     efuse_power_offset_stru pwr_offset;      /* 功率校准数据 */
147     osal_u16 rssi_offset;                    /* rssi校准数据 */
148     osal_u8 temp;                            /* 产测温度档位 */
149     osal_u8 resv2;
150 } efuse_mfg_data_stru;
151 
152 typedef struct {
153     osal_char efuse_name[EFUSE_NAME_LEN];
154     osal_u8 id[EFUSE_GROUP_MAX];
155     osal_u8 lock_id[EFUSE_GROUP_MAX];
156     osal_u8 bit_pos;
157 } efuse_id_info_stru;
158 
159 osal_void hal_rf_set_default_cmu_xo_trim(osal_void);
160 osal_void hal_set_mfg_mode(osal_u8 mode);
161 osal_void hal_set_xo_trim_coarse(osal_u32 xo_trim_coarse, osal_u32 *coarse_reg);
162 osal_void hal_set_xo_trim_fine(osal_u32 xo_trim_fine, osal_u32 *fine_reg);
163 osal_void hal_get_xo_trim(osal_u32 *xo_trim_coarse, osal_u32 *xo_trim_fine);
164 osal_void hal_get_temp(osal_void);
165 osal_s32 hal_config_efuse_operate(efuse_operate_stru *param);
166 osal_s32 hal_read_efuse_cmu_xo_trim(osal_u8 *coarse_reg, osal_u8 *fine_reg);
167 osal_s32 hal_efuse_cmu_xo_trim_write(osal_u8 coarse_reg, osal_u8 fine_reg);
168 osal_s32 hal_set_efuse_rssi_offset(osal_u8 *rssi_param, osal_u32 len);
169 osal_s32 hal_get_efuse_rssi_offset(osal_void);
170 osal_s32 hal_efuse_write_temp(osal_u8 gears);
171 osal_s32 hal_efuse_read_temp(osal_void);
172 osal_s32 hal_efuse_status(osal_void);
173 osal_s32 hal_efuse_write_power_info(osal_s32 *power_info, osal_u32 len);
174 osal_s32 hal_read_efuse_read_power_info(osal_void);
175 #ifdef __cplusplus
176 #if __cplusplus
177 }
178 #endif
179 #endif
180 #endif
181 #endif
182 #endif
183