1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_HAL_DDC_H__ 19 #define __HDMI_HAL_DDC_H__ 20 21 #include "drv_hdmi_common.h" 22 #include "hdmi_reg_aon.h" 23 #include "hdmi_product_define.h" 24 25 #define DDC_MAX_RECORD_NUM 30 26 #define DDC_DEFAULT_TIMEOUT_ACCESS 100 27 #define DDC_DEFAULT_TIMEOUT_HPD 100 28 #define DDC_DEFAULT_TIMEOUT_IN_PROG 20 29 #define DDC_DEFAULT_TIMEOUT_SCL 1 30 #define DDC_DEFAULT_TIMEOUT_SDA 30 31 #define DDC_DEFAULT_TIMEOUT_ISSUE 20 32 #define DDC_DEFAULT_RETRY_TIMEOUT_ISSUE 60 33 34 typedef enum { 35 DDC_FUNC_TYPE_EDID, 36 DDC_FUNC_TYPE_HDCP, 37 DDC_FUNC_TYPE_SCDC, 38 DDC_FUNC_TYPE_BUTT 39 } ddc_func_type; 40 41 typedef enum { 42 DDC_MASTER_MODE_PWD, 43 DDC_MASTER_MODE_AON 44 } ddc_master_mode; 45 46 typedef enum { 47 DDC_MODE_READ_SINGLE_NO_ACK, 48 DDC_MODE_READ_SINGLE_ACK, 49 DDC_MODE_READ_MUTIL_NO_ACK, 50 DDC_MODE_READ_MUTIL_ACK, 51 DDC_MODE_READ_SEGMENT_NO_ACK, 52 DDC_MODE_READ_SEGMENT_ACK, 53 DDC_MODE_WRITE_MUTIL_NO_ACK, 54 DDC_MODE_WRITE_MUTIL_ACK, 55 DDC_MODE_BUTT 56 } ddc_issue_mode; 57 58 typedef struct { 59 hi_bool valid; 60 ddc_mst_ctrl ddc_ctrl; /* 4040 */ 61 ddc_fifo_rdata ddc_rdata; /* 4044 */ 62 ddc_fifo_wdata ddc_wdata; /* 4048 */ 63 ddc_data_cnt data_count; /* 404C */ 64 ddc_slave_cfg slave_cfg; /* 4050 */ 65 ddc_mst_state mst_state; /* 4054 */ 66 ddc_mst_cmd mst_cmd; /* 4058 */ 67 ddc_man_ctrl ddc_sw_ctrl; /* 405C */ 68 ddc_state_clr state_clr; /* 4060 */ 69 } ddc_reg_status; 70 71 typedef union { 72 struct { 73 hi_u32 access_wait_timeout : 1; 74 hi_u32 bus_low_scl : 1; 75 hi_u32 bus_low_sda : 1; 76 hi_u32 err_isseu_mode : 1; 77 hi_u32 issue_timeout : 1; 78 hi_u32 bus_no_ack : 1; 79 hi_u32 in_prog_timeout : 1; 80 hi_u32 hpd_no_exist : 1; 81 hi_u32 clr_err_fail : 1; 82 hi_u32 reserved : 23; 83 } u32; 84 hi_u32 word; 85 } ddc_err; 86 87 typedef struct { 88 hi_u8 segment; 89 hi_u8 offset; 90 ddc_func_type func_type; 91 ddc_issue_mode issue_mode; 92 ddc_master_mode master_mode; /* AON MODE ONLY FOR DEBUG */ 93 hi_u32 speed; 94 hi_u32 access_timeout; 95 hi_u32 hpd_timeout; 96 hi_u32 in_prog_timeout; 97 hi_u32 scl_timeout; 98 hi_u32 sda_timeout; 99 hi_u32 issue_timeout; 100 hi_s32 data_size; 101 hi_u8 *data; 102 } ddc_cfg; 103 104 typedef struct { 105 hi_bool init; /* is the DDC init */ 106 hi_u32 elem_ptr; /* element pointer in the record array */ 107 hi_u32 total_num; /* total record size, max value is DDC_MAX_RECORD_NUM */ 108 } ddc_run; 109 110 typedef struct { 111 hi_u64 start_time; 112 hi_u64 time_len; 113 ddc_err un_err; 114 ddc_reg_status reg_before; 115 ddc_reg_status reg_after; 116 ddc_cfg cfg; 117 hi_s32 data_size; 118 hi_u8 *data; 119 } ddc_record_elem; 120 121 typedef struct { 122 ddc_run run; 123 ddc_record_elem ddc_record[DDC_MAX_RECORD_NUM]; 124 osal_semaphore_t ddc_wr_mutex; 125 } ddc_info; 126 127 hi_s32 hal_hdmi_ddc_init(hdmi_device_id hdmi); 128 129 hi_s32 hal_hdmi_ddc_deinit(hdmi_device_id hdmi); 130 131 hi_s32 hal_hdmi_ddc_issue(hdmi_device_id hdmi, ddc_cfg *cfg); 132 133 hi_void hal_hdmi_ddc_default_cfg_get(hdmi_device_id hdmi, ddc_cfg *cfg); 134 135 hi_s32 hal_hdmi_ddc_edid_raw_get(hdmi_device_id hdmi, hi_s32 size, hi_u8 *data); 136 137 #endif /* __HDMI_HAL_DDC_H__ */ 138 139