1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_HAL_PHY_H__ 19 #define __HDMI_HAL_PHY_H__ 20 21 #include "hdmi_hal_intf.h" 22 #include "drv_hdmi_common.h" 23 24 typedef enum { 25 PHY_RPRE_50, 26 PHY_RPRE_56, 27 PHY_RPRE_71, 28 PHY_RPRE_83, 29 PHY_RPRE_100, 30 PHY_RPRE_125, 31 PHY_RPRE_250, 32 PHY_RPRE_500, 33 PHY_RPRE_BUTT 34 } phy_rpre; 35 36 typedef enum { 37 PHY_RTERM_MODE_SINGLE, 38 PHY_RTERM_MODE_SOURCE, 39 PHY_RTERM_MODE_LOAD, 40 PHY_RTERM_MODE_DOUBLEDIFF, 41 PHY_RTERM_MODE_BUTT 42 } phy_rterm_mode; 43 44 typedef struct { 45 hi_u32 ssc_amptd; // 1/1M 46 hi_u32 ssc_freq; // 1hz 47 } phy_ssc_cfg; 48 49 typedef struct { 50 hi_bool ssc_enable; 51 hi_bool ssc_debug_en; 52 phy_ssc_cfg ssc_cfg; 53 } hdmi_phy_ssc; 54 55 typedef struct { 56 hi_u32 pix_clk; /* pixel colck, in k_hz */ 57 hi_u32 tmds_clk; /* TMDS colck, in k_hz */ 58 hdmi_deep_color deep_color; /* deep color(color depth) */ 59 hdmi_phy_ssc phy_ssc; /* spread spectrum ctrl(ssc) para */ 60 } hdmi_phy_ssc_cfg; 61 62 typedef struct { 63 hi_u32 i_de_main_clk; 64 hi_u32 i_de_main_d0; 65 hi_u32 i_de_main_d1; 66 hi_u32 i_de_main_d2; 67 hi_u32 i_main_clk; 68 hi_u32 i_main_d0; 69 hi_u32 i_main_d1; 70 hi_u32 i_main_d2; 71 hi_u32 i_de_pre_clk; 72 hi_u32 i_de_pre_d0; 73 hi_u32 i_de_pre_d1; 74 hi_u32 i_de_pre_d2; 75 hi_u32 i_pre_clk; 76 hi_u32 i_pre_d0; 77 hi_u32 i_pre_d1; 78 hi_u32 i_pre_d2; 79 phy_rpre r_de_pre_clk; 80 phy_rpre r_de_pre_d0; 81 phy_rpre r_de_pre_d1; 82 phy_rpre r_de_pre_d2; 83 phy_rpre r_pre_clk; 84 phy_rpre r_pre_d0; 85 phy_rpre r_pre_d1; 86 phy_rpre r_pre_d2; 87 phy_rterm_mode r_term_mode_clk; 88 hi_u32 r_term_clk; 89 phy_rterm_mode r_term_mode_d0; 90 hi_u32 r_term_d0; 91 phy_rterm_mode r_term_mode_d1; 92 hi_u32 r_term_d1; 93 phy_rterm_mode r_term_mode_d2; 94 hi_u32 r_term_d2; 95 } phy_hw_spec_cfg; 96 97 typedef enum { 98 PHY_FEEDTHRU_CAP_DELAY_18, 99 PHY_FEEDTHRU_CAP_DELAY_35, 100 PHY_FEEDTHRU_CAP_DELAY_45, 101 PHY_FEEDTHRU_CAP_DELAY_55 102 } phy_feedthru_cap_delay; 103 104 /* HW spec struct new version, HI3531DV200 */ 105 typedef struct { 106 hi_u32 i_demain_clk; 107 hi_u32 i_demain_d0; 108 hi_u32 i_demain_d1; 109 hi_u32 i_demain_d2; 110 hi_u32 i_main_clk; 111 hi_u32 i_main_d0; 112 hi_u32 i_main_d1; 113 hi_u32 i_main_d2; 114 hi_bool feedthru_cap_clk_en; 115 hi_bool feedthru_cap_d0_en; 116 hi_bool feedthru_cap_d1_en; 117 hi_bool feedthru_cap_d2_en; 118 phy_feedthru_cap_delay feedthru_cap_delay_clk; 119 phy_feedthru_cap_delay feedthru_cap_delay_d0; 120 phy_feedthru_cap_delay feedthru_cap_delay_d1; 121 phy_feedthru_cap_delay feedthru_cap_delay_d2; 122 phy_rterm_mode rterm_mode_clk; 123 hi_u32 rterm_clk; 124 phy_rterm_mode rterm_mode_d0; 125 hi_u32 rterm_d0; 126 phy_rterm_mode rterm_mode_d1; 127 hi_u32 rterm_d1; 128 phy_rterm_mode rterm_mode_d2; 129 hi_u32 rterm_d2; 130 hi_u32 vcm_sel; 131 } phy_hwspec_enhance_cfg; 132 133 typedef struct { 134 hi_bool hw_spec_debug_en; 135 phy_hw_spec_cfg spec_cfg; 136 phy_hwspec_enhance_cfg enhance_cfg; 137 } hdmi_phy_hw_spec; 138 139 typedef struct { 140 hi_u32 tmds_clk; /* TMDS colck, in k_hz */ 141 hdmi_trace_len trace_len; 142 hdmi_phy_hw_spec hdmi_phy_spec; /* phy specification para */ 143 } hdmi_phy_hw_spec_cfg; 144 145 typedef struct { 146 hi_u32 pixel_clk; 147 hi_u32 tmds_clk; /* TMDS colck, in k_hz */ 148 hi_bool emi_enable; 149 hdmi_deep_color deep_color; /* deep color(color depth) */ 150 hdmi_phy_mode_cfg mode_cfg; /* TMDS/FRL/tx_ffe */ 151 hdmi_trace_len trace_len; 152 } hdmi_phy_tmds_cfg; 153 154 typedef struct { 155 hi_bool init; 156 hi_bool power_enable; 157 hi_bool oe_enable; 158 hdmi_phy_tmds_cfg tmds_cfg; 159 hdmi_phy_ssc ssc_cfg; 160 phy_hw_spec_cfg hw_spec_cfg; 161 hdmi_hw_spec hw_spec; 162 phy_hwspec_enhance_cfg spec_enhance_cfg; 163 } hdmi_phy_info; 164 165 typedef struct { 166 hdmi_hw_spec hw_spec_cfg; 167 hdmi_hw_spec hw_spec_def; 168 hdmi_hw_param hw_param_cur; 169 } hdmi_phy_hw_param; 170 171 hi_s32 hal_hdmi_phy_init(const hdmi_hal_init *hal_init); 172 173 hi_s32 hal_hdmi_phy_deinit(hi_void); 174 175 hi_void hal_hdmi_phy_reset(hi_void); 176 177 hi_s32 hal_hdmi_phy_power_get(hi_bool *enable); 178 179 hi_void hal_hdmi_phy_power_set(hi_bool enable); 180 181 hi_void hal_hdmi_phy_oe_set(hi_bool enable); 182 183 hi_s32 hal_hdmi_phy_oe_get(hi_bool *enable); 184 185 hi_s32 hal_hdmi_phy_tmds_set(hdmi_phy_tmds_cfg *tmds_cfg); 186 187 hi_s32 hal_hdmi_phy_spec_set(hdmi_phy_hw_spec_cfg *hdmi_spec_cfg); 188 189 hi_s32 hal_hdmi_phy_info_get(hdmi_phy_info *phy_status); 190 191 hi_void hal_hdmi_phy_ssc_set(hdmi_phy_ssc_cfg *hdmi_ssc_cfg); 192 193 hi_s32 hal_hdmi_phy_ssc_get(hi_bool *enable); 194 195 hi_s32 hal_hdmi_phy_params_set(hi_u32 tmds_clk, const hdmi_hw_spec *hw_spec); 196 197 hi_s32 hal_hdmi_phy_params_get(hdmi_phy_hw_param *hw_param); 198 199 #endif /* __HDMI_HAL_PHY_H__ */ 200 201