1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_HAL_SCDC_H__ 19 #define __HDMI_HAL_SCDC_H__ 20 21 #include "hi_type.h" 22 #include "hdmi_hal_machine.h" 23 #include "hdmi_hal_ddc.h" 24 #include "drv_hdmi_common.h" 25 #include "hdmi_product_define.h" 26 27 #define SCDC_DEFAULT_SCRAMBLE_TIMEOUT 200 28 #define SCDC_MAX_SCRAMBLE_TIMEOUT 1000 29 #define SCDC_DEFAULT_SCRAMBLE_INTERVAL 20 30 #define SCDC_DEFAULT_POLL_INTERVAL 150 31 #define SCDC_MAX_UPDATE_RECORD_NUM 3 32 #define SCDC_WHILE_SCRAMBLE_TIMEOUT 3500 33 #define SCDC_ERROR_MAX_NUM_SCRAMBLE 3 34 #define SCDC_ERROR_MAX_NUM_OE_DISABLE 3 35 #define SCDC_ERROR_MAX_NUM_OE_ENABLE 3 36 #define SCDC_ERROR_MAX_NUM_RR_TEST 3 37 #define SCDC_ERROR_MAX_NUM_SINK_UNREAD 1 38 #define SCDC_GET_SCRAMBLE_STATUS_TIME 1 39 #define SCDC_OE_DISABLE_WAIT_TIME 5 40 #define SCDC_MAX_ERROR_RECORD_NUM (SCDC_ERROR_MAX_NUM_SCRAMBLE + \ 41 SCDC_ERROR_MAX_NUM_OE_DISABLE + SCDC_ERROR_MAX_NUM_OE_ENABLE) 42 43 /* HDMI2.0 section 10.4.1.3, OFFSET 0x10 */ 44 typedef union { 45 struct { 46 hi_u8 status_update : 1; 47 hi_u8 ced_update : 1; 48 hi_u8 rr_test : 1; 49 hi_u8 rsvd : 5; 50 } u8; 51 hi_u8 byte; 52 } scdc_updata_flag; 53 54 /* HDMI2.0 section 10.4.1.4, OFFSET 0x20 */ 55 typedef union { 56 struct { 57 hi_u8 screambling_enable : 1; 58 hi_u8 tmds_bit_clock_ratio : 1; 59 hi_u8 rsvd : 6; 60 } u8; 61 hi_u8 byte; 62 } scdc_tmds_config; 63 64 /* HDMI2.0 section 10.4.1.5, OFFSET 0x21 */ 65 typedef union { 66 struct { 67 hi_u8 screambling_status : 1; 68 hi_u8 rsvd : 7; 69 } u8; 70 hi_u8 byte; 71 } scdc_scrambler_status; 72 73 /* HDMI2.0 section 10.4.1.6, OFFSET 0x30 */ 74 typedef union { 75 struct { 76 hi_u8 rr_enable : 1; 77 hi_u8 rsvd : 7; 78 } u8; 79 hi_u8 byte; 80 } scdc_config0; 81 82 /* HDMI2.0 section 10.4.1.7, OFFSET 0x40 */ 83 typedef union { 84 struct { 85 hi_u8 colck_detected : 1; 86 hi_u8 ch0_locked : 1; 87 hi_u8 ch1_locked : 1; 88 hi_u8 ch2_locked : 1; 89 hi_u8 rsvd : 4; 90 } u8; 91 hi_u8 byte; 92 } scdc_status_flag0; 93 94 /* HDMI2.0 section 10.4.1.8, OFFSET 0x50~0x55 */ 95 typedef union { 96 struct { 97 hi_u8 ch_error_cnt_l : 8; 98 hi_u8 ch_error_cnt_h : 7; 99 hi_u8 ch_valid : 1; 100 } u16; 101 hi_u16 word; 102 } scdc_char_err_detect; 103 104 /* HDMI2.0 section 10.4.1.9, OFFSET 0xC0 */ 105 typedef union { 106 struct { 107 hi_u8 test_read_request_delay : 7; 108 hi_u8 test_read_request : 1; 109 } u8; 110 hi_u8 byte; 111 } scdc_rr_test_cfg; 112 113 typedef enum { 114 SCDC_OFFSET_SINK_VERSION = 0x01, 115 SCDC_OFFSET_SRC_VERSION = 0x02, 116 SCDC_OFFSET_UPDATE_0 = 0x10, 117 SCDC_OFFSET_UPDATE_1 = 0x11, 118 SCDC_OFFSET_TMDS_CONFIG = 0x20, 119 SCDC_OFFSET_SCRAMBLER_STATUS = 0x21, 120 SCDC_OFFSET_CONFIG_0 = 0x30, 121 SCDC_OFFSET_STATUS_FLAG_0 = 0x40, 122 SCDC_OFFSET_STATUS_FLAG_1 = 0x41, 123 SCDC_OFFSET_DRR_DET_0_L = 0x50, 124 SCDC_OFFSET_DRR_DET_0_H = 0x51, 125 SCDC_OFFSET_DRR_DET_1_L = 0x52, 126 SCDC_OFFSET_DRR_DET_1_H = 0x53, 127 SCDC_OFFSET_DRR_DET_2_L = 0x54, 128 SCDC_OFFSET_DRR_DET_2_H = 0x55, 129 SCDC_OFFSET_DRR_DET_CHKSUM = 0x56, 130 SCDC_OFFSET_TEST_CONFIG_0 = 0xC0, 131 SCDC_OFFSET_IEEE_OUI_3TH = 0xD0, 132 SCDC_OFFSET_IEEE_OUI_2ND = 0xD1, 133 SCDC_OFFSET_IEEE_OUI_1ST = 0xD2, 134 SCDC_OFFSET_DEVICE_ID_HEAD = 0xD3, 135 SCDC_OFFSET_DEVICE_ID_TAIL = 0xDD 136 } scdc_offset; 137 138 typedef struct { 139 hi_u8 sink_version; // SCDC_OFFSET_SINK_VERSION 140 hi_u8 src_version; // SCDC_OFFSET_SRC_VERSION 141 scdc_tmds_config tmds_config0; // SCDC_OFFSET_TMDS_CONFIG 142 scdc_config0 config0; // SCDC_OFFSET_CONFIG_0 143 scdc_rr_test_cfg rr_test_cfg; // SCDC_OFFSET_TEST_CONFIG_0 144 hi_u8 ieee_out[SCDC_OFFSET_IEEE_OUI_1ST - SCDC_OFFSET_IEEE_OUI_3TH + 1]; 145 hi_u8 device_id[SCDC_OFFSET_DEVICE_ID_TAIL - SCDC_OFFSET_DEVICE_ID_HEAD + 1]; 146 } scdc_reg_static_status; 147 148 typedef struct { 149 scdc_updata_flag update0; // SCDC_OFFSET_UPDATE_0 150 scdc_scrambler_status scramble_status; // SCDC_OFFSET_SCRAMBLER_STATUS 151 scdc_status_flag0 status_flag0; // SCDC_OFFSET_STATUS_FLAG_0 152 scdc_char_err_detect ch0_err; // SCDC_OFFSET_DRR_stb_det_0_L,SCDC_OFFSET_DRR_stb_det_0_H 153 scdc_char_err_detect ch1_err; // SCDC_OFFSET_DRR_stb_det_1_L,SCDC_OFFSET_DRR_stb_det_1_H 154 scdc_char_err_detect ch2_err; // SCDC_OFFSET_DRR_stb_det_2_L,SCDC_OFFSET_DRR_stb_det_2_H 155 hi_u8 err_chk_sum; // SCDC_OFFSET_DRR_stb_det_CHKSUM 156 } scdc_updata_status; 157 158 typedef struct { 159 hi_bool sink_read_quest; 160 /* HI_TRUE indicate enable; HI_FALSE indicate disable. */ 161 hi_bool src_scramble; 162 /* HI_TRUE indicate enable; HI_FALSE indicate disable. */ 163 hi_bool sink_scramble; 164 /* HI_TRUE indicate 40x; HI_FALSE indicate 10x. */ 165 hi_bool tmds_clk_ratio40x; 166 /* in unit of ms. for [0,200],force to default 200; or, set the value cfg(>200). */ 167 hi_u32 scramble_timeout; 168 /* in unit of ms, range[20,200).for [0,20] or >=200,force to default 20; or, set the value cfg[20,200). */ 169 hi_u32 scramble_interval; 170 } scdc_attr; 171 172 typedef enum { 173 SCDC_ERROR_SINK_UNREAD, 174 SCDC_ERROR_SCRAMBLE, 175 SCDC_ERROR_OE_DISABLE, 176 SCDC_ERROR_OE_ENABLE, 177 SCDC_ERROR_BUTT 178 } scdc_error_type; 179 180 typedef struct { 181 hi_u32 sramble_fail_cnt; 182 hi_u32 oe_disable_fail_cnt; 183 hi_u32 oe_enable_fail_cnt; 184 hi_u32 sink_un_read_cnt; 185 } scdc_error_cnt; 186 187 typedef struct { 188 scdc_error_type err_type; 189 hi_u64 time_stamp; 190 scdc_attr err_attr; 191 } scdc_error_record; 192 193 typedef struct { 194 hi_bool init; 195 hdmi_device_id hdmi_id; 196 hi_u32 mach_id; 197 hi_bool mach_enable; 198 hi_u64 mach_interval; 199 scdc_error_cnt err_cnt; 200 hi_u32 err_record_ptr; 201 scdc_error_record err_record[SCDC_MAX_ERROR_RECORD_NUM]; 202 hi_u32 reg_update_ptr; 203 scdc_updata_status reg_update[SCDC_MAX_UPDATE_RECORD_NUM]; 204 scdc_reg_static_status reg_static; 205 } scdc_status; 206 207 typedef struct { 208 scdc_status status; 209 scdc_attr attr; 210 } scdc_infomation; 211 212 hi_s32 hal_hdmi_scdc_init(hdmi_device_id hdmi_id); 213 214 hi_s32 hal_hdmi_scdc_deinit(hdmi_device_id hdmi_id); 215 216 hi_s32 hal_hdmi_scdc_reset(hdmi_device_id hdmi_id); 217 218 hi_s32 hal_hdmi_scdc_attr_set(hdmi_device_id hdmi_id, scdc_attr *attr); 219 220 hi_s32 hal_hdmi_scdc_attr_get(hdmi_device_id hdmi_id, scdc_attr *attr); 221 222 hi_s32 hal_hdmi_scdc_all_status_get(hdmi_device_id hdmi_id, scdc_status *status); 223 224 hi_s32 hal_hdmi_scdc_support_get(hdmi_device_id hdmi_id, hi_bool *support); 225 226 hi_s32 hal_hdmi_scdc_scramble_force(hdmi_device_id hdmi_id, hi_bool enable); 227 228 hi_s32 hal_hdmi_scdc_mach_enable(hdmi_device_id hdmi_id, hi_bool enable); 229 230 #endif /* __HDMI_HAL_SCDC_H__ */ 231 232