1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_REG_CTRL_H__ 19 #define __HDMI_REG_CTRL_H__ 20 21 #include "hi_type.h" 22 23 typedef union { 24 struct { 25 unsigned int tx_pwd_srst_req : 1; /* [0] */ 26 unsigned int tx_sys_srst_req : 1; /* [1] */ 27 unsigned int tx_vid_srst_req : 1; /* [2] */ 28 unsigned int tx_hdmi_srst_req : 1; /* [3] */ 29 unsigned int tx_hdcp1x_srst_req : 1; /* [4] */ 30 unsigned int tx_phy_srst_req : 1; /* [5] */ 31 unsigned int tx_aud_srst_req : 1; /* [6] */ 32 unsigned int tx_acr_srst_req : 1; /* [7] */ 33 unsigned int tx_afifo_srst_req : 1; /* [8] */ 34 unsigned int tx_hdcp2x_srst_req : 1; /* [9] */ 35 unsigned int tx_mcu_srst_req : 1; /* [10] */ 36 unsigned int rsv_0 : 21; /* [31:11] */ 37 } bits; 38 unsigned int u32; 39 } tx_pwd_rst_ctrl; 40 41 typedef union { 42 struct { 43 unsigned int scdc_ddcm_abort : 1; /* [0] */ 44 unsigned int scdc_access_en : 1; /* [1] */ 45 unsigned int scdc_auto_reply : 1; /* [2] */ 46 unsigned int scdc_auto_poll : 1; /* [3] */ 47 unsigned int scdc_auto_reply_stop : 1; /* [4] */ 48 unsigned int scdc_poll_sel : 1; /* [5] */ 49 unsigned int scdc_hdcp_det_en : 1; /* [6] */ 50 unsigned int scdc_stall_req : 1; /* [7] */ 51 unsigned int rsv_1 : 24; /* [31:8] */ 52 } bits; 53 unsigned int u32; 54 } scdc_fsm_ctrl; 55 56 typedef union { 57 struct { 58 unsigned int scdc_poll_timer : 22; /* [21:0] */ 59 unsigned int rsv_2 : 10; /* [31:22] */ 60 } bits; 61 unsigned int u32; 62 } scdc_poll_timerl; 63 64 typedef union { 65 struct { 66 unsigned int scdc_fsm_state : 4; /* [3:0] */ 67 unsigned int scdc_rreq_state : 4; /* [7:4] */ 68 unsigned int scdc_active : 1; /* [8] */ 69 unsigned int scdc_in_prog : 1; /* [9] */ 70 unsigned int scdc_rreq_in_prog : 1; /* [10] */ 71 unsigned int rsv_3 : 21; /* [31:11] */ 72 } bits; 73 unsigned int u32; 74 } scdc_fsm_state; 75 76 typedef union { 77 struct { 78 unsigned int scdc_flag_byte0 : 8; /* [7:0] */ 79 unsigned int scdc_flag_byte1 : 8; /* [15:8] */ 80 unsigned int rsv_4 : 16; /* [31:16] */ 81 } bits; 82 unsigned int u32; 83 } scdc_flag_byte; 84 85 typedef union { 86 struct { 87 unsigned int pwd_fifo_data_out : 8; /* [7:0] */ 88 unsigned int rsv_5 : 24; /* [31:8] */ 89 } bits; 90 unsigned int u32; 91 } pwd_fifo_rdata; 92 93 typedef union { 94 struct { 95 unsigned int pwd_fifo_data_in : 8; /* [7:0] */ 96 unsigned int rsv_6 : 24; /* [31:8] */ 97 } bits; 98 unsigned int u32; 99 } pwd_fifo_wdata; 100 101 typedef union { 102 struct { 103 unsigned int pwd_fifo_data_cnt : 5; /* [4:0] */ 104 unsigned int rsv_7 : 3; /* [7:5] */ 105 unsigned int pwd_data_out_cnt : 10; /* [17:8] */ 106 unsigned int rsv_8 : 14; /* [31:18] */ 107 } bits; 108 unsigned int u32; 109 } pwd_data_cnt; 110 111 typedef union { 112 struct { 113 unsigned int pwd_slave_addr : 8; /* [7:0] */ 114 unsigned int pwd_slave_offset : 8; /* [15:8] */ 115 unsigned int pwd_slave_seg : 8; /* [23:16] */ 116 unsigned int rsv_9 : 8; /* [31:24] */ 117 } bits; 118 unsigned int u32; 119 } pwd_slave_cfg; 120 121 typedef union { 122 struct { 123 unsigned int pwd_i2c_no_ack : 1; /* [0] */ 124 unsigned int pwd_i2c_bus_low : 1; /* [1] */ 125 unsigned int pwd_i2c_in_prog : 1; /* [2] */ 126 unsigned int pwd_fifo_wr_in_use : 1; /* [3] */ 127 unsigned int pwd_fifo_rd_in_use : 1; /* [4] */ 128 unsigned int pwd_fifo_empty : 1; /* [5] */ 129 unsigned int pwd_fifo_half_full : 1; /* [6] */ 130 unsigned int pwd_fifo_full : 1; /* [7] */ 131 unsigned int rsv_10 : 24; /* [31:8] */ 132 } bits; 133 unsigned int u32; 134 } pwd_mst_state; 135 136 typedef union { 137 struct { 138 unsigned int pwd_mst_cmd : 4; /* [3:0] */ 139 unsigned int rsv_11 : 28; /* [31:4] */ 140 } bits; 141 unsigned int u32; 142 } pwd_mst_cmd; 143 144 typedef union { 145 struct { 146 unsigned int pwd_clr_bus_low : 1; /* [0] */ 147 unsigned int pwd_clr_no_ack : 1; /* [1] */ 148 unsigned int rsv_12 : 30; /* [31:2] */ 149 } bits; 150 unsigned int u32; 151 } pwd_mst_clr; 152 153 typedef union { 154 struct { 155 unsigned int cpu_ddc_force_req : 1; /* [0] */ 156 unsigned int reg_auto_abort_en : 1; /* [1] */ 157 unsigned int rsv_13 : 30; /* [31:2] */ 158 } bits; 159 unsigned int u32; 160 } ddc_mst_arb_ctrl; 161 162 typedef union { 163 struct { 164 unsigned int cpu_ddc_req : 1; /* [0] */ 165 unsigned int rsv_14 : 31; /* [31:1] */ 166 } bits; 167 unsigned int u32; 168 } ddc_mst_arb_reql; 169 170 typedef union { 171 struct { 172 unsigned int cpu_ddc_req_ack : 1; /* [0] */ 173 unsigned int rsv_15 : 31; /* [31:1] */ 174 } bits; 175 unsigned int u32; 176 } ddc_mst_arb_ack; 177 178 typedef union { 179 struct { 180 unsigned int ddc_arb_state : 9; /* [8:0] */ 181 unsigned int rsv_16 : 23; /* [31:9] */ 182 } bits; 183 unsigned int u32; 184 } ddc_mst_arb_state; 185 186 typedef union { 187 struct { 188 unsigned int tx_pwd_intr_state : 1; /* [0] */ 189 unsigned int rsv_17 : 31; /* [31:1] */ 190 } bits; 191 unsigned int u32; 192 } tx_pwd_intr_state; 193 194 typedef union { 195 struct { 196 unsigned int tx_sys_intr_state : 1; /* [0] */ 197 unsigned int vidpath_intr_state : 1; /* [1] */ 198 unsigned int audpath_intr_state : 1; /* [2] */ 199 unsigned int txhdmi_intr_state : 1; /* [3] */ 200 unsigned int txhdcp_intr_state : 1; /* [4] */ 201 unsigned int hdcp2x_intr_state : 1; /* [5] */ 202 unsigned int rsv_18 : 26; /* [31:6] */ 203 } bits; 204 unsigned int u32; 205 } pwd_sub_intr_state; 206 207 typedef union { 208 struct { 209 unsigned int tx_sys_intr_mask : 1; /* [0] */ 210 unsigned int vidpath_intr_mask : 1; /* [1] */ 211 unsigned int audpath_intr_mask : 1; /* [2] */ 212 unsigned int txhdmi_intr_mask : 1; /* [3] */ 213 unsigned int txhdcp_intr_mask : 1; /* [4] */ 214 unsigned int hdcp2x_intr_mask : 1; /* [5] */ 215 unsigned int rsv_19 : 26; /* [31:6] */ 216 } bits; 217 unsigned int u32; 218 } pwd_sub_intr_mask; 219 220 typedef union { 221 struct { 222 unsigned int tx_sys_intr_state0 : 1; /* [0] */ 223 unsigned int tx_sys_intr_state1 : 1; /* [1] */ 224 unsigned int tx_sys_intr_state2 : 1; /* [2] */ 225 unsigned int tx_sys_intr_state3 : 1; /* [3] */ 226 unsigned int tx_sys_intr_state4 : 1; /* [4] */ 227 unsigned int tx_sys_intr_state5 : 1; /* [5] */ 228 unsigned int rsv_20 : 26; /* [31:6] */ 229 } bits; 230 unsigned int u32; 231 } txsys_intr_state; 232 233 typedef union { 234 struct { 235 unsigned int tx_sys_intr_mask0 : 1; /* [0] */ 236 unsigned int tx_sys_intr_mask1 : 1; /* [1] */ 237 unsigned int tx_sys_intr_mask2 : 1; /* [2] */ 238 unsigned int tx_sys_intr_mask3 : 1; /* [3] */ 239 unsigned int tx_sys_intr_mask4 : 1; /* [4] */ 240 unsigned int tx_sys_intr_mask5 : 1; /* [5] */ 241 unsigned int rsv_21 : 26; /* [31:6] */ 242 } bits; 243 unsigned int u32; 244 } txsys_intr_mask; 245 246 typedef union { 247 struct { 248 unsigned int vidpath_intr_state0 : 1; /* [0] */ 249 unsigned int vidpath_intr_state1 : 1; /* [1] */ 250 unsigned int vidpath_intr_state2 : 1; /* [2] */ 251 unsigned int vidpath_intr_state3 : 1; /* [3] */ 252 unsigned int vidpath_intr_state4 : 1; /* [4] */ 253 unsigned int vidpath_intr_state5 : 1; /* [5] */ 254 unsigned int vidpath_intr_state6 : 1; /* [6] */ 255 unsigned int rsv_22 : 25; /* [31:7] */ 256 } bits; 257 unsigned int u32; 258 } video_path_intr_state; 259 260 typedef union { 261 struct { 262 unsigned int vidpath_intr_mask0 : 1; /* [0] */ 263 unsigned int vidpath_intr_mask1 : 1; /* [1] */ 264 unsigned int vidpath_intr_mask2 : 1; /* [2] */ 265 unsigned int vidpath_intr_mask3 : 1; /* [3] */ 266 unsigned int vidpath_intr_mask4 : 1; /* [4] */ 267 unsigned int vidpath_intr_mask5 : 1; /* [5] */ 268 unsigned int vidpath_intr_mask6 : 1; /* [6] */ 269 unsigned int rsv_23 : 25; /* [31:7] */ 270 } bits; 271 unsigned int u32; 272 } video_path_intr_mask; 273 274 typedef union { 275 struct { 276 unsigned int audpath_intr_state0 : 1; /* [0] */ 277 unsigned int audpath_intr_state1 : 1; /* [1] */ 278 unsigned int audpath_intr_state2 : 1; /* [2] */ 279 unsigned int audpath_intr_state3 : 1; /* [3] */ 280 unsigned int audpath_intr_state4 : 1; /* [4] */ 281 unsigned int audpath_intr_state5 : 1; /* [5] */ 282 unsigned int audpath_intr_state6 : 1; /* [6] */ 283 unsigned int audpath_intr_state7 : 1; /* [7] */ 284 unsigned int audpath_intr_state8 : 1; /* [8] */ 285 unsigned int rsv_24 : 23; /* [31:9] */ 286 } bits; 287 unsigned int u32; 288 } audio_path_intr_state; 289 290 typedef union { 291 struct { 292 unsigned int audpath_intr_mask0 : 1; /* [0] */ 293 unsigned int audpath_intr_mask1 : 1; /* [1] */ 294 unsigned int audpath_intr_mask2 : 1; /* [2] */ 295 unsigned int audpath_intr_mask3 : 1; /* [3] */ 296 unsigned int audpath_intr_mask4 : 1; /* [4] */ 297 unsigned int audpath_intr_mask5 : 1; /* [5] */ 298 unsigned int audpath_intr_mask6 : 1; /* [6] */ 299 unsigned int audpath_intr_mask7 : 1; /* [7] */ 300 unsigned int audpath_intr_mask8 : 1; /* [8] */ 301 unsigned int rsv_25 : 23; /* [31:9] */ 302 } bits; 303 unsigned int u32; 304 } audio_path_intr_mask; 305 306 typedef union { 307 struct { 308 unsigned int txhdmi_intr_state0 : 1; /* [0] */ 309 unsigned int rsv_26 : 31; /* [31:1] */ 310 } bits; 311 unsigned int u32; 312 } txhdmi_intr_state; 313 314 typedef union { 315 struct { 316 unsigned int txhdmi_intr_mask0 : 1; /* [0] */ 317 unsigned int rsv_27 : 31; /* [31:1] */ 318 } bits; 319 unsigned int u32; 320 } txhdmi_intr_mask; 321 322 typedef union { 323 struct { 324 unsigned int hdcp_intr_state0 : 1; /* [0] */ 325 unsigned int hdcp_intr_state1 : 1; /* [1] */ 326 unsigned int rsv_28 : 30; /* [31:2] */ 327 } bits; 328 unsigned int u32; 329 } hdcp_intr_state; 330 331 typedef union { 332 struct { 333 unsigned int hdcp_intr_mask0 : 1; /* [0] */ 334 unsigned int hdcp_intr_mask1 : 1; /* [1] */ 335 unsigned int rsv_29 : 30; /* [31:2] */ 336 } bits; 337 unsigned int u32; 338 } hdcp_intr_mask; 339 340 typedef struct { 341 unsigned int reserved_0[4]; /* 0-C */ 342 volatile tx_pwd_rst_ctrl pwd_rst_ctrl; /* 10 */ 343 volatile scdc_fsm_ctrl fsm_ctrl; /* 14 */ 344 volatile scdc_poll_timerl poll_timer; /* 18 */ 345 volatile scdc_fsm_state fsm_state; /* 1C */ 346 volatile scdc_flag_byte flag; /* 20 */ 347 unsigned int reserved_1[5]; /* 0-c */ 348 volatile pwd_fifo_rdata rdata; /* 38 */ 349 volatile pwd_fifo_wdata wdata; /* 3C */ 350 volatile pwd_data_cnt data_cnt; /* 40 */ 351 volatile pwd_slave_cfg slave_cfg; /* 44 */ 352 volatile pwd_mst_state mst_state; /* 48 */ 353 volatile pwd_mst_cmd mst_cmd; /* 4C */ 354 volatile pwd_mst_clr mst_clr; /* 50 */ 355 unsigned int reserved_2[4]; /* 54-60 */ 356 volatile ddc_mst_arb_ctrl ddc_arb_ctrl; /* 64 */ 357 volatile ddc_mst_arb_reql ddc_arb_req; /* 68 */ 358 volatile ddc_mst_arb_ack ddc_arb_ack; /* 6C */ 359 volatile ddc_mst_arb_state ddc_arb_state; /* 70 */ 360 unsigned int reserved_3[35]; /* 74-FC */ 361 volatile tx_pwd_intr_state pwd_irq_state; /* 100 */ 362 volatile pwd_sub_intr_state sub_irq_state; /* 104 */ 363 volatile pwd_sub_intr_mask sub_irq_mask; /* 108 */ 364 volatile txsys_intr_state sys_irq_state; /* 10C */ 365 volatile txsys_intr_mask sys_irq_mask; /* 110 */ 366 volatile video_path_intr_state video_irq_state; /* 114 */ 367 volatile video_path_intr_mask video_irq_mask; /* 118 */ 368 volatile audio_path_intr_state audio_irq_state; /* 11C */ 369 volatile audio_path_intr_mask audio_irq_mask; /* 120 */ 370 volatile txhdmi_intr_state hdmi_irq_state; /* 124 */ 371 volatile txhdmi_intr_mask hdmi_irq_mask; /* 128 */ 372 volatile hdcp_intr_state hdcp_irq_state; /* 12C */ 373 volatile hdcp_intr_mask hdcp_irq_mask; /* 130 */ 374 } hdmi_reg_tx_ctrl; 375 376 int hdmi_reg_tx_ctrl_regs_init(char *addr); 377 int hdmi_reg_tx_ctrl_regs_deinit(void); 378 int hdmi_reg_tx_afifo_srst_req_set(unsigned int tx_afifo_srst_req); 379 int hdmi_reg_tx_acr_srst_req_set(unsigned int tx_acr_srst_req); 380 int hdmi_reg_tx_aud_srst_req_set(unsigned int tx_aud_srst_req); 381 int hdmi_reg_tx_hdmi_srst_req_set(unsigned int tx_hdmi_srst_req); 382 int hdmi_reg_tx_pwd_srst_req_set(unsigned int tx_pwd_srst_req); 383 int hdmi_reg_pwd_fifo_data_in_set(unsigned int pwd_fifo_data_in); 384 int hdmi_reg_pwd_data_out_cnt_set(unsigned int pwd_data_out_cnt); 385 int hdmi_reg_pwd_slave_addr_set(unsigned int pwd_slave_addr); 386 int hdmi_reg_pwd_slave_offset_set(unsigned int pwd_slave_offset); 387 int hdmi_reg_pwd_slave_seg_set(unsigned int pwd_slave_seg); 388 int hdmi_reg_pwd_mst_cmd_set(unsigned int pwd_mst_cmd); 389 int hdmi_reg_cpu_ddc_req_set(unsigned int cpu_ddc_req); 390 int hdmi_reg_tx_mcu_srst_req_set(unsigned int tx_mcu_srst_req); 391 hi_u8 hdmi_reg_rdata_pwd_fifo_data_out_get(void); 392 hi_u32 hdmi_reg_pwd_fifo_data_out_get(void); 393 hi_u32 hdmi_reg_pwd_i2c_in_prog_get(void); 394 hi_u32 hdmi_reg_pwd_fifo_empty_get(void); 395 hi_u32 hdmi_reg_cpu_ddc_req_ack_get(void); 396 397 #endif /* __HDMI_REG_CTRL_H__ */ 398 399