1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: Default memory configurations 15 * 16 * Create: 2021-06-16 17 */ 18 19 #ifndef MEMORY_CONFIG_COMMON_H 20 #define MEMORY_CONFIG_COMMON_H 21 22 /** 23 * @defgroup connectivity_config_memory MEMORY 24 * @ingroup connectivity_config 25 * @{ 26 */ 27 28 #if defined(CONFIG_RADAR_SENSOR_RX_MEM_8K) 29 #define RADAR_SENSOR_RX_MEM_SIZE 0x2000 30 #elif defined(CONFIG_RADAR_SENSOR_RX_MEM_16K) 31 #define RADAR_SENSOR_RX_MEM_SIZE 0x4000 32 #elif defined(CONFIG_RADAR_SENSOR_RX_MEM_24K) 33 #define RADAR_SENSOR_RX_MEM_SIZE 0x6000 34 #elif defined(CONFIG_RADAR_SENSOR_RX_MEM_32K) 35 #define RADAR_SENSOR_RX_MEM_SIZE 0x8000 36 #else 37 #define RADAR_SENSOR_RX_MEM_SIZE 0x2000 /* default 8K */ 38 #endif 39 40 /* Bootrom config */ 41 #define BOOTROM_START 0x100000 42 #define BOOTROM_LENGTH 0x9000 /* 36K */ 43 44 /* ROM config */ 45 #define ROM_START 0x109000 46 #define ROM_LENGTH 0x43000 /* 268K = 304K - 36K(bootrom) */ 47 48 /* APP ITCM config */ 49 #define APP_ITCM_ORIGIN 0x14C000 50 #define APP_ITCM_REGION_LEN 0x34000 /* 208K */ 51 52 /* APP DTCM config */ 53 #define APP_DTCM_ORIGIN 0x180000 54 #define APP_DTCM_REGION_LEN 0x48000 /* 288K */ 55 56 #define PRESERVED_REGION_LENGTH (0x100) 57 58 /* APP share_ram config */ 59 #define APP_SRAM_ORIGIN 0xA00000 60 61 #if defined(CONFIG_BGLE_RAM_SIZE_16K) && defined(WIFI_TCM_OPTIMIZE) 62 // pkt_ram 512K itcm: 64K dtcm: 16K bgle: 16K 63 #define APP_ITCM_LENGTH 0x10000 /* 64K */ 64 #define APP_DTCM_LENGTH 0x4000 /* 16K */ 65 #define APP_SRAM_LENGTH (0x80000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 512K - RADAR - PRESERVED */ 66 67 #elif defined(CONFIG_BGLE_RAM_SIZE_16K) 68 // pkt_ram 544K itcm: 32K dtcm: 16K bgle: 16K 69 #define APP_ITCM_LENGTH 0x4000 /* 16K */ 70 #define APP_DTCM_LENGTH 0x8000 /* 32K */ 71 #define APP_SRAM_LENGTH (0x88000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 544K - RADAR - PRESERVED */ 72 73 #elif defined(CONFIG_BGLE_RAM_SIZE_32K) 74 // pkt_ram 544K itcm: 16K dtcm: 16K bgle: 32K 75 #define APP_ITCM_LENGTH 0x4000 /* 16K */ 76 #define APP_DTCM_LENGTH 0x4000 /* 16K */ 77 #define APP_SRAM_LENGTH (0x88000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 544K - RADAR - PRESERVED */ 78 79 #elif defined(CONFIG_BGLE_RAM_SIZE_64K) // btc-only target 80 // pkt_ram 448K itcm: 32K dtcm: 64K bgle: 64K 81 #define APP_ITCM_LENGTH 0x8000 /* 32K */ 82 #define APP_DTCM_LENGTH 0x10000 /* 64K */ 83 #define APP_SRAM_LENGTH (0x70000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 448K - RADAR - PRESERVED */ 84 85 #elif defined(WIFI_TCM_OPTIMIZE) // wifi-only target 86 // pkt_ram 512K itcm: 64K dtcm: 32K bgle: 0K 87 #define APP_ITCM_LENGTH 0x10000 /* 64K */ 88 #define APP_DTCM_LENGTH 0x8000 /* 32K */ 89 #define APP_SRAM_LENGTH (0x80000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 512K - RADAR - PRESERVED */ 90 91 #else 92 // pkt_ram 576K itcm: 16K dtcm: 16K bgle: 0K 93 #define APP_ITCM_LENGTH 0x4000 /* 16K */ 94 #define APP_DTCM_LENGTH 0x4000 /* 16K */ 95 #define APP_SRAM_LENGTH (0x90000 - RADAR_SENSOR_RX_MEM_SIZE - PRESERVED_REGION_LENGTH) /* 576K - RADAR - PRESERVED */ 96 #endif 97 98 #define PRESERVED_REGION_ORIGIN (APP_SRAM_ORIGIN + APP_SRAM_LENGTH) 99 100 #define RADAR_SENSOR_RX_MEM_START (APP_SRAM_ORIGIN + APP_SRAM_LENGTH + PRESERVED_REGION_LENGTH) 101 #define RADAR_SENSOR_RX_MEM_END (RADAR_SENSOR_RX_MEM_START + RADAR_SENSOR_RX_MEM_SIZE) 102 103 /* Flash config */ 104 #define FLASH_START 0x200000 105 #define FLASH_LEN 0x800000 /* 8M */ 106 #define FLASH_MAX_END (FLASH_START + FLASH_LEN) 107 108 #define APP_PROGRAM_ORIGIN (0x230000 + 0x300) 109 #ifdef CONFIG_SUPPORT_HILINK_INDIE_UPGRADE 110 #define APP_PROGRAM_LENGTH (0x240000 - 0x300) 111 #else 112 #define APP_PROGRAM_LENGTH (0x200000 - 0x300) 113 #endif 114 115 #ifdef CONFIG_SUPPORT_HILINK_INDIE_UPGRADE 116 #define HILINK_SRAM_LENGTH (0x16000 - 36 * 1024) 117 #define HILINK_STARTUP_LENGTH 0x6A000 118 #else 119 #define HILINK_SRAM_LENGTH 0x0 120 #define HILINK_STARTUP_LENGTH 0x0 121 #endif 122 123 #define HILINK_SRAM_ORIGIN (APP_SRAM_ORIGIN + APP_SRAM_LENGTH - HILINK_SRAM_LENGTH) 124 #define HILINK_STARTUP_ORIGIN (APP_PROGRAM_ORIGIN + APP_PROGRAM_LENGTH - HILINK_STARTUP_LENGTH) 125 126 #define HILINK_PROGRAM_ORIGIN (HILINK_STARTUP_ORIGIN + 0x300) 127 #define HILINK_PROGRAM_LENGTH (HILINK_STARTUP_LENGTH - 0x300) 128 129 /* ----------------------------------------------------------------------------------------------------------------- */ 130 /* APP RAM defines 131 * APP has base 512K ITCM (Instruction TCM) for code 132 * 256K DTCM (Data TCM) for DATA. 133 * APP ITCM VECTORS TABLE 134 * RAM TEXT 135 * 136 * APP DTCM STACK 137 * RAM 138 */ 139 /* 256K DTCM for APP core data */ 140 /* stack for normal 8k */ 141 #define APP_USER_STACK_BASEADDR APP_SRAM_ORIGIN 142 #define APP_USER_STACK_LEN 0x1000 143 #define APP_USER_STACK_LIMIT (APP_USER_STACK_BASEADDR + APP_USER_STACK_LEN) 144 145 /* stack for irq 1k */ 146 #define APP_IRQ_STACK_BASEADDR APP_USER_STACK_LIMIT 147 #define APP_IRQ_STACK_LEN 0x800 148 #define APP_IRQ_STACK_LIMIT (APP_IRQ_STACK_BASEADDR + APP_IRQ_STACK_LEN) 149 150 /* stack for exception 1k */ 151 #define APP_EXCP_STACK_BASEADDR APP_IRQ_STACK_LIMIT 152 #define APP_EXCP_STACK_LEN 0x800 153 #define APP_EXCP_STACK_LIMIT (APP_EXCP_STACK_BASEADDR + APP_EXCP_STACK_LEN) 154 155 /* stack for nmi 1k */ 156 #define APP_NMI_STACK_BASEADDR APP_EXCP_STACK_LIMIT 157 #define APP_NMI_STACK_LEN 0x400 158 #define APP_NMI_STACK_LIMIT (APP_NMI_STACK_BASEADDR + APP_NMI_STACK_LEN) 159 160 #define APP_RAM_ORIGIN (APP_NMI_STACK_LIMIT) 161 #define APP_RAM_END (APP_SRAM_ORIGIN + APP_SRAM_LENGTH) 162 #define APP_RAM_LENGTH (APP_RAM_END - APP_RAM_ORIGIN) 163 164 #define SHARED_MEM_START 0 165 #define SHARED_MEM_LENGTH 0 166 #define MCPU_TRACE_MEM_REGION_START 0 167 #define CPU_TRACE_MEM_REGION_LENGTH 0 168 #define BT_RAM_ORIGIN_APP_MAPPING 0 169 #define BT_RAM_ORIGIN_APP_MAPPING_LENGTH 0 170 #define BCPU_TRACE_MEM_REGION_START 0 171 #define CPU_TRACE_MEM_REGION_LENGTH 0 172 173 #ifdef CONFIG_MEMORY_CUSTOMIZE_RSV 174 #define APP_PROGRAM_MEM_RSV_ORIGIN 0x5FA000 // must be 4K aligned 175 #endif 176 177 /** 178 * @} 179 */ 180 #endif