1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * otpdefs.h SROM/OTP definitions. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id$ 28 */ 29 30 #ifndef _OTPDEFS_H_ 31 #define _OTPDEFS_H_ 32 33 /* SFLASH */ 34 #define SFLASH_ADDRESS_OFFSET_4368 0x1C000000u 35 #define SFLASH_SKU_OFFSET_4368 0xEu 36 #define SFLASH_MACADDR_OFFSET_4368 0x4u 37 /* 38 * In sflash based chips, first word in sflash says the length. 39 * So only default value is defined here. Actual length is read 40 * from sflash in dhdpcie_srom_sflash_health_chk 41 * 0x0521 * 2 .x2 since length says number of words. 42 */ 43 #define SFLASH_LEN_4368 0xA42u 44 45 #define SROM_ADDRESS_OFFSET_4355 0x0800u 46 #define SROM_ADDRESS_OFFSET_4364 0xA000u 47 #define SROM_ADDRESS_OFFSET_4377 0x0800u 48 #define SROM_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) 49 #define SROM_MACADDR_OFFSET_4355 0x84u 50 #define SROM_MACADDR_OFFSET_4364 0x82u 51 #define SROM_MACADDR_OFFSET_4377 0xE2u 52 #define SROM_SKU_OFFSET_4355 0x8Au 53 #define SROM_SKU_OFFSET_4364 0x8Cu 54 #define SROM_SKU_OFFSET_4377 0xECu 55 #define SROM_CAL_SIG1_OFFSET_4355 0xB8u 56 #define SROM_CAL_SIG2_OFFSET_4355 0xBAu 57 #define SROM_CAL_SIG1_OFFSET_4364 0xA0u 58 #define SROM_CAL_SIG2_OFFSET_4364 0xA2u 59 #define SROM_CAL_SIG1 0x4c42u 60 #define SROM_CAL_SIG2 0x424fu 61 #define SROM_LEN_4355 512u 62 #define SROM_LEN_4364 2048u 63 #define SROM_LEN_4377 2048u 64 65 #define OTP_USER_AREA_OFFSET_4355 0xC0u 66 #define OTP_USER_AREA_OFFSET_4364 0xC0u 67 #define OTP_USER_AREA_OFFSET_4368 0x120u 68 #define OTP_USER_AREA_OFFSET_4377 0x120u 69 #define OTP_OFFSET_4368 0x5000u 70 #define OTP_OFFSET_4377 0x11000u 71 #define OTP_CTRL1_VAL 0xFA0000 72 #define OTP_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) 73 #define OTP_VERSION_TUPLE_ID 0x15 74 #define OTP_VENDOR_TUPLE_ID 0x80 75 #define OTP_CIS_REGION_END_TUPLE_ID 0XFF 76 77 #define PCIE_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0x3000) 78 #define SPROM_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_CTRL) 79 #define SPROM_CTRL_OPCODE_READ_MASK 0x9FFFFFFF 80 #define SPROM_CTRL_START_BUSY_MASK 0x80000000 81 #define SPROM_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_ADDRESS) 82 #define SPROM_DATA(sih) (SI_ENUM_BASE(sih) + CC_SROM_DATA) 83 #define OTP_CTRL1_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0xF4) 84 #define PMU_MINRESMASK_REG_ADDR(sih) (SI_ENUM_BASE(sih) + MINRESMASKREG) 85 #define CHIP_COMMON_STATUS_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CHIPST) 86 #define CHIP_COMMON_CLKDIV2_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CLKDIV2) 87 88 #define CC_CLKDIV2_SPROMDIV_MASK 0x7u 89 #define CC_CLKDIV2_SPROMDIV_VAL 0X4u 90 #define CC_CHIPSTATUS_STRAP_BTUART_MASK 0x40u 91 #define PMU_OTP_PWR_ON_MASK 0xC47 92 #define PMU_PWRUP_DELAY 500 /* in us */ 93 #define DONGLE_TREFUP_PROGRAM_DELAY 5000 /* 5ms in us */ 94 #define SPROM_BUSY_POLL_DELAY 5 /* 5us */ 95 96 typedef enum { 97 BCM4355_IDX = 0, 98 BCM4364_IDX, 99 BCM4368_IDX, 100 BCM4377_IDX, 101 BCMMAX_IDX 102 } chip_idx_t; 103 104 typedef enum { 105 BCM4368_BTOP_IDX, 106 BCM4377_BTOP_IDX, 107 BCMMAX_BTOP_IDX 108 } chip_idx_btop_t; 109 110 typedef enum { 111 BCM4368_SFLASH_IDX, 112 BCMMAX_SFLASH_IDX 113 } chip_idx_sflash_t; 114 115 extern uint32 otp_addr_offsets[]; 116 extern uint32 otp_usrarea_offsets[]; 117 extern uint32 sku_offsets[]; 118 extern uint32 srf_addr_offsets[]; 119 extern uint32 supported_chips[]; 120 121 char *dhd_get_plat_sku(void); 122 #endif /* _OTPDEFS_H */ 123