1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: WS63 Application Core Platform Definitions 15 * 16 * Create: 2021-06-16 17 */ 18 19 #ifndef PLATFORM_CORE_H 20 #define PLATFORM_CORE_H 21 22 #include "chip_core_definition.h" 23 #include "platform_core_rom.h" 24 25 /** 26 * @defgroup DRIVER_PLATFORM_CORE CHIP Platform CORE Driver 27 * @ingroup DRIVER_PLATFORM 28 * @{ 29 */ 30 #ifndef YES 31 #define YES (1) 32 #endif 33 34 #ifndef NO 35 #define NO (0) 36 #endif 37 38 extern unsigned int get_hso_buff(void); 39 #define LOGGING_REGION_START get_hso_buff() 40 #define LOGGING_REGION_LENGTH 0x1000 41 42 #define GLB_CTL_M_RB_BASE 0x40002000 43 #define GLB_CTL_B_RB_BASE 0x57000400 44 #define GLB_CTL_D_RB_BASE 0x57000800 45 #define DISPLAY_CTL_RB_BASE 0x56000000 46 #define GPU_BASE_ADDR 0x56200000 47 #define DSS_BASE_ADDR 0x56100000 48 49 #define B_CTL_RB_BASE 0x59000000 50 #define M_CTL_RB_BASE 0x52000000 51 #define COM_CTL_RB_BASE 0x55000000 52 #define PMU1_CTL_RB_BASE 0x40003000 53 #define PMU2_CMU_CTL_RB_BASE 0x57008000 54 #define ULP_AON_CTL_RB_ADDR 0x5702c000 55 #define FUSE_CTL_RB_ADDR 0x57028000 56 #define XO_CORE_TRIM_REG 0x57028308 57 #define XO_CORE_CTRIM_REG 0x5702830c 58 #define XIP_CACHE_CTL 0xA3006000 59 #define NMI_CTL_REG_BASE_ADDR 0x52000700 60 61 #define FLASH_START_ADDR 0x200000 62 63 #define UART0_BASE 0x44010004 /* UART_L0 */ 64 #define UART1_BASE 0x44011004 /* UART_H0 */ 65 #define UART2_BASE 0x44012004 /* UART_H1 */ 66 #define DMA_BASE_ADDR 0x4A000000 /* M_DMA */ 67 #define SDMA_BASE_ADDR 0x520A0000 /* S_DMA */ 68 69 /* I2C reg base addr */ 70 #define I2C_BUS_0_BASE_ADDR 0x44018000 71 #define I2C_BUS_1_BASE_ADDR 0x44018100 72 73 /* spi reg base addr */ 74 #define SPI_BUS_0_BASE_ADDR 0x44020000 // SPI_M0 75 #define SPI_BUS_1_BASE_ADDR 0x44021000 // QSPI_0 76 77 #define I2S_BUS_0_BASE_ADDR 0x4402503C 78 79 #define DMA_HANDSHAKE_I2C_BUS_0_TX HAL_DMA_HANDSHAKING_I2C0_TX 80 #define DMA_HANDSHAKE_I2C_BUS_0_RX HAL_DMA_HANDSHAKING_I2C0_RX 81 #define DMA_HANDSHAKE_I2C_BUS_1_TX HAL_DMA_HANDSHAKING_I2C1_TX 82 #define DMA_HANDSHAKE_I2C_BUS_1_RX HAL_DMA_HANDSHAKING_I2C1_RX 83 #define DMA_HANDSHAKE_I2C_BUS_2_TX HAL_DMA_HANDSHAKING_I2C2_TX 84 #define DMA_HANDSHAKE_I2C_BUS_2_RX HAL_DMA_HANDSHAKING_I2C2_RX 85 #define DMA_HANDSHAKE_I2C_BUS_3_TX HAL_DMA_HANDSHAKING_I2C3_TX 86 #define DMA_HANDSHAKE_I2C_BUS_3_RX HAL_DMA_HANDSHAKING_I2C3_RX 87 #define DMA_HANDSHAKE_I2C_BUS_4_TX HAL_DMA_HANDSHAKING_I2C4_TX 88 #define DMA_HANDSHAKE_I2C_BUS_4_RX HAL_DMA_HANDSHAKING_I2C4_RX 89 90 #define HAL_SPI_DEVICE_MODE_SET_REG (*(volatile unsigned short *)(0x44000250)) 91 #define HAL_SPI3_MODE_SET_REG (M_CTL_RB_BASE + 0x950) 92 93 /* PWM reg base addr */ 94 #define PWM_0_BASE 0x44024000 95 96 /* PWM INTR REG */ 97 #define PWM_INTR_ENABLE_REG (*(volatile unsigned short *)0x52000900) 98 #define PWM_INTR_CLEAR_REG (*(volatile unsigned short *)0x52000904) 99 #define PWM_INTR_STATUS_REG (*(volatile unsigned short *)0x52000908) 100 101 // GPIO regs 102 #define GPIO_CHANNEL_0_BASE_ADDR 0x44028000 103 #define GPIO_CHANNEL_1_BASE_ADDR 0x44029000 104 #define GPIO_CHANNEL_2_BASE_ADDR 0x4402A000 105 106 #define ULP_GPIO_BASE_ADDR 0x57030000 // ULP GPIO 107 108 // GPIO select core 109 #define HAL_GPIO_D_CORE_SET_REG 0x570001B0 110 #define HAL_GPIO_NON_D_CORE_SET_REG 0x57000180 111 #define HAL_GPIO_CORE_SET_CHANNEL_OFFSET 0x08 112 #define HAL_GPIO_CORE_SET_REG_OFFSET 2 113 #define HAL_GPIO_CORE_SET_GPIOS 16 114 115 // ULP GPIO int clk config 116 #define HAL_GPIO_ULP_AON_GP_REG 0x5702C010 117 #define HAL_GPIO_ULP_AON_PCLK_INT_EN_BIT 0 118 #define HAL_GPIO_ULP_AON_PCLK_INT_CLK_SEL_BIT 1 119 #define HAL_GPIO_ULP_PCLK_INTR_STATUS_BITS 0x3 120 121 #define RTC_TIMER_BASE_ADDR 0x57024000 122 123 #define SYSTICK_BASE_ADDR 0x40005000 124 125 #define AFE_DIG_BASE_ADDRESS 0x57036000 126 127 #define HAL_SOFT_RST_CTL_BASE (GLB_CTL_M_RB_BASE) 128 #define HAL_GLB_CTL_M_ATOP1_L_REG_OFFSET 0x100 129 #define HAL_CHIP_WDT_ATOP1_RST_BIT 4 130 131 // SEC BASE ADDR 132 #define SEC_CTL_RB_BASE 0x52009000 133 #define RSAV2_S_RB_BASE 0x52009900 134 #define TRNG_RB_BASE 0x52009800 135 136 // cpu trace memory 137 #define TRACE_MEM_REGION_START MCPU_TRACE_MEM_REGION_START 138 #define TRACE_MEM_REGION_LENGTH CPU_TRACE_MEM_REGION_LENGTH 139 140 /* 141 * Maximum UART buses 142 * Defined here rather than in the uart_bus_t enum, due to needing to use it for conditional compilation 143 */ 144 #define UART_BUS_MAX_NUMBER 3 // !< Max number of UARTS available 145 #define I2C_BUS_MAX_NUMBER 2 // !< Max number of I2C available 146 147 #define SPI_BUS_MAX_NUMBER 2 // !< Max number of SPI available 148 #define GPIO_MAX_NUMBER 3 // !< Max number of GPIO available 149 #define I2S_MAX_NUMBER 1 150 151 #define S_DMA_CHANNEL_MAX_NUM 4 // !< Max number of SM_DMA available 152 #define B_DMA_CHANNEL_MAX_NUM 8 // !< Max number of M_DMA available 153 154 #define DMA_CHANNEL_MAX_NUM (S_DMA_CHANNEL_MAX_NUM + B_DMA_CHANNEL_MAX_NUM) 155 156 #define CHIP_BCPU_SWDDIO 0 157 #define CHIP_BCPU_SWDCLK 0 158 159 #define TEST_SUITE_UART_BUS CONFIG_TESTSUIT_UART // UART H0 160 /* Test Suite UART Transmission PIN to use */ 161 #define TEST_SUITE_UART_TX_PIN S_AGPIO9 162 /* Test Suite UART Reception PIN to use */ 163 #define TEST_SUITE_UART_RX_PIN S_AGPIO10 164 165 #ifdef PRE_ASIC 166 #ifdef SW_UART_DEBUG 167 #define CHIP_FIXED_RX_PIN S_AGPIO14 168 #define CHIP_FIXED_TX_PIN S_AGPIO15 169 #else 170 #define CHIP_FIXED_RX_PIN ULP_GPIO1 171 #define CHIP_FIXED_TX_PIN ULP_GPIO0 172 #endif 173 #else 174 #if defined(DEVICE_ONLY) 175 #define CHIP_FIXED_TX_PIN S_AGPIO18 // S_MGPIO9 176 #define CHIP_FIXED_RX_PIN S_AGPIO19 // S_MGPIO10 177 #else 178 #define CHIP_FIXED_TX_PIN S_AGPIO9 179 #define CHIP_FIXED_RX_PIN S_AGPIO10 180 #endif 181 #endif 182 #define SW_DEBUG_UART_BUS CONFIG_DEBUG_UART 183 #define CHIP_FIXED_UART_BUS CONFIG_WVT_UART 184 #define CODELOADER_UART_BUS UART_BUS_0 185 #define CODELOADER_UART_TX_PIN S_AGPIO15 186 #define CODELOADER_UART_RX_PIN S_AGPIO14 187 188 #define LOG_UART_BUS CONFIG_LOG_UART 189 #define LOG_UART_TX_PIN S_AGPIO12 // S_AGPIO18 190 #define LOG_UART_RX_PIN S_AGPIO13 // S_AGPIO19 191 192 #define AT_UART_BUS CONFIG_AT_UART 193 194 #define QSPI_MAX_NUMBER 2 195 #define FLASH_QSPI_ID QSPI_BUS_1 196 #define QSPI_0_BASE_ADDR 0xA3000000 197 #define QSPI_1_BASE_ADDR 0xA3002000 198 199 /* !< QSPI bus */ 200 typedef enum { 201 QSPI_BUS_0 = 0, 202 QSPI_BUS_1, 203 QSPI_BUS_NONE = QSPI_MAX_NUMBER 204 } qspi_bus_t; 205 206 /** 207 * @brief UART bus. 208 */ 209 typedef enum { // !< Hi1132 | Hi1135 210 UART_BUS_0 = 0, // !< UART L | UART L0 211 #if UART_BUS_MAX_NUMBER > 1 212 UART_BUS_1 = 1, // !< UART H | UART H0 213 #endif 214 #if UART_BUS_MAX_NUMBER > 2 215 UART_BUS_2 = 2, // !< M UART | UART H1 216 #endif 217 UART_BUS_NONE = UART_BUS_MAX_NUMBER // !< Value used as invalid/unused UART number 218 } uart_bus_t; 219 220 /** 221 * @brief I2C bus. 222 */ 223 typedef enum { 224 I2C_BUS_0, // !< I2C0 225 I2C_BUS_1, // !< I2C1 226 #if I2C_BUS_MAX_NUMBER > 2 227 I2C_BUS_2, // !< I2C2 228 #if I2C_BUS_MAX_NUMBER > 3 // !< I2C3 229 I2C_BUS_3 = 3, 230 I2C_BUS_4 = 4, 231 #endif 232 #endif 233 I2C_BUS_NONE = I2C_BUS_MAX_NUMBER 234 } i2c_bus_t; 235 236 /*************************************** 237 For WS63 config: 238 SPI_M0, 239 SPI_MS_1, 240 SPI_MS_2, 241 SPI_MS_3, 242 SPI_S_4, 243 QSPI_0, 244 QSPI_1 245 ***************************************/ 246 /** 247 * @brief Definition of SPI bus index. 248 */ 249 typedef enum { 250 SPI_BUS_0 = 0, 251 SPI_BUS_1, 252 SPI_BUS_2, 253 SPI_BUS_3, 254 SPI_BUS_4, 255 SPI_BUS_5, 256 SPI_BUS_6, 257 SPI_BUS_NONE = SPI_BUS_MAX_NUMBER 258 } spi_bus_t; 259 260 261 /** 262 * @brief SIO(I2S/PCM) Bus. 263 * 264 */ 265 typedef enum { 266 SIO_BUS_0, 267 SIO_NONE = I2S_MAX_NUMBER 268 } sio_bus_t; 269 270 /* !< SLAVE CPU */ 271 typedef enum { 272 SLAVE_CPU_BT, 273 SLAVE_CPU_MAX_NUM, 274 } slave_cpu_t; 275 276 /**********************************************************************/ 277 /************************* MPU config base addr ***********************/ 278 /**********************************************************************/ 279 // config register region 280 #define MPU_REG_ADDR0_BASE 0x50000000 281 #define MPU_REG_ADDR0_LEN 0x10000000 282 283 #define MPU_REG_ADDR1_BASE 0xA3000000 284 #define MPU_REG_ADDR1_LEN 0x01000000 285 286 // ROM region 287 #define MPU_ROM_ADDR_BASE 0x0 288 #define MPU_ROM_ADDR_LEN 0x8000 289 290 // ITCM region 291 #define MPU_ITCM_ADDR_BASE 0x80000 292 #define MPU_ITCM_ADDR_LEN 0x80000 293 294 // L2ram region 295 #define MPU_L2RAM_ADDR0_BASE 0x100000 296 #define MPU_L2RAM_ADDR0_LEN 0x100000 297 #define MPU_L2RAM_ADDR1_BASE 0x200000 298 #define MPU_L2RAM_ADDR1_LEN 0x100000 299 300 // XIP PSRAM read & execute region 301 #define MPU_XIP_PSRAM_RO_ADDR_BASE 0x08000000 302 #define MPU_XIP_PSRAM_RO_ADDR_LEN 0x04000000 303 304 // XIP PSRAM bypass(read/write) region 305 #define MPU_XIP_PSRAM_RW_ADDR_BASE 0x0C000000 306 #define MPU_XIP_PSRAM_RW_ADDR_LEN 0x04000000 307 308 // XIP NorFlash region 309 #define MPU_XIP_FLASE_RO_ADDR_BASE 0x10000000 310 #define MPU_XIP_FLASE_RO_ADDR_LEN 0x10000000 311 312 // Sharemem region 313 #define MPU_SHAREMEM_ADDR_BASE 0x87000000 314 #define MPU_SHAREMEM_ADDR_LEN 0x10000 315 316 // MDMA(m0) address judge 317 #define MEM_X2P_MEMORY_START 0xA3000000 318 #define MEM_X2P_MEMORY_END 0xA3008FFF 319 #define L2RAM_MEMORY_START 0x00100000 320 #define L2RAM_MEMORY_END 0x0035FFFF 321 #define QSPI_XIP_MEMORY_START 0x08000000 322 #define QSPI_XIP_MEMORY_END 0x1FFFFFFF 323 324 // CHIP RESET offset address 325 #define CHIP_RESET_OFF 0x110 326 327 // Power on the flash memory on the FPGA 328 #define PMU_RESERV1 0x570040C8 329 #define HI_SFC_REG_BASE 0x48000000 330 #define HI_SFC_FLASH1_BASE 0x48100000 331 #define HI_SFC_MEM_SIZE 0x00800000 332 333 334 // 适配旧GPIO号定义 335 #define S_MGPIO0 0 // GPIO0_0 C_PINMUX_CTL offset: 0x0300 336 #define S_MGPIO1 1 // GPIO0_1 C_PINMUX_CTL 337 #define S_MGPIO2 2 // GPIO0_2 C_PINMUX_CTL 338 #define S_MGPIO3 3 // GPIO0_3 C_PINMUX_CTL 339 #define S_MGPIO4 4 // GPIO0_4 C_PINMUX_CTL 340 #define S_MGPIO5 5 // GPIO0_5 C_PINMUX_CTL 341 #define S_MGPIO6 6 // GPIO0_6 C_PINMUX_CTL 342 #define S_MGPIO7 7 // GPIO0_7 C_PINMUX_CTL 343 #define S_MGPIO8 8 // GPIO0_8 C_PINMUX_CTL 344 #define S_MGPIO9 9 // GPIO0_9 C_PINMUX_CTL 345 #define S_MGPIO10 10 // GPIO0_10 C_PINMUX_CTL 346 #define S_MGPIO11 11 // GPIO0_11 C_PINMUX_CTL 347 #define S_MGPIO12 12 // GPIO0_12 C_PINMUX_CTL 348 #define S_MGPIO13 13 // GPIO0_13 C_PINMUX_CTL 349 #define S_MGPIO14 14 // GPIO0_14 C_PINMUX_CTL 350 #define S_MGPIO15 15 // GPIO0_15 C_PINMUX_CTL 351 #define S_MGPIO16 16 // GPIO0_16 C_PINMUX_CTL 352 #define S_MGPIO17 17 // GPIO0_17 C_PINMUX_CTL 353 #define S_MGPIO18 18 // GPIO0_18 C_PINMUX_CTL 354 #define S_MGPIO19 19 // GPIO0_19 C_PINMUX_CTL 355 #define S_MGPIO20 20 // GPIO0_20 C_PINMUX_CTL 356 #define S_MGPIO21 21 // GPIO0_21 C_PINMUX_CTL 357 #define S_MGPIO22 22 // GPIO0_22 C_PINMUX_CTL 358 #define S_MGPIO23 23 // GPIO0_23 C_PINMUX_CTL 359 #define S_MGPIO24 24 // GPIO0_24 C_PINMUX_CTL 360 #define S_MGPIO25 25 // GPIO0_25 C_PINMUX_CTL 361 #define S_MGPIO26 26 // GPIO0_26 C_PINMUX_CTL 362 #define S_MGPIO27 27 // GPIO0_27 C_PINMUX_CTL 363 #define S_MGPIO28 28 // GPIO0_28 C_PINMUX_CTL offset: 0x031C 364 #define S_MGPIO29 29 // GPIO0_29 C_PINMUX_CTL 365 #define S_MGPIO30 30 // GPIO0_30 C_PINMUX_CTL 366 #define S_MGPIO31 31 // GPIO0_31 C_PINMUX_CTL 367 368 #define S_AGPIO0 32 // GPIO1_0 PINMUX_CTL offset: 0x0320 369 #define S_AGPIO1 33 // GPIO1_1 PINMUX_CTL 370 #define S_AGPIO2 34 // GPIO1_2 PINMUX_CTL 371 #define S_AGPIO3 35 // GPIO1_3 PINMUX_CTL 372 #define S_AGPIO4 36 // GPIO1_4 PINMUX_CTL offset: 0x0324 373 #define S_AGPIO5 37 // GPIO1_5 PINMUX_CTL 374 #define S_AGPIO6 38 // GPIO1_6 PINMUX_CTL 375 #define S_AGPIO7 39 // GPIO1_7 PINMUX_CTL 376 #define S_AGPIO8 40 // GPIO1_8 PINMUX_CTL offset: 0x0328 377 #define S_AGPIO9 41 // GPIO1_9 PINMUX_CTL 378 #define S_AGPIO10 42 // GPIO1_10 PINMUX_CTL 379 #define S_AGPIO11 43 // GPIO1_11 PINMUX_CTL 380 #define S_AGPIO12 44 // GPIO1_12 PINMUX_CTL offset: 0x032C 381 #define S_AGPIO13 45 // GPIO1_13 PINMUX_CTL 382 #define S_AGPIO14 46 // GPIO1_14 PINMUX_CTL 383 #define S_AGPIO15 47 // GPIO1_15 PINMUX_CTL 384 #define S_AGPIO16 48 // GPIO1_16 PINMUX_CTL offset: 0x0330 385 #define S_AGPIO17 49 // GPIO1_17 PINMUX_CTL 386 #define S_AGPIO18 50 // GPIO1_18 PINMUX_CTL 387 #define S_AGPIO19 51 // GPIO1_19 PINMUX_CTL 388 389 #define S_HGPIO0 52 // GPIO1_20 C_PINMUX_CTL offset: 0x0334 390 #define S_HGPIO1 53 // GPIO1_21 C_PINMUX_CTL 391 #define S_HGPIO2 54 // GPIO1_22 C_PINMUX_CTL 392 #define S_HGPIO3 55 // GPIO1_23 C_PINMUX_CTL 393 #define S_HGPIO4 56 // GPIO1_24 C_PINMUX_CTL offset: 0x0338 394 #define S_HGPIO5 57 // GPIO1_25 C_PINMUX_CTL 395 396 #define L_HGPIO0 64 // RESERVED 397 #define L_HGPIO11 75 // RESERVED 398 399 #define L_AGPIO0 76 // GPIO2_12 PINMUX_CTL offset: 0x034C 400 #define L_AGPIO1 77 // GPIO2_13 PINMUX_CTL 401 #define L_AGPIO2 78 // GPIO2_14 PINMUX_CTL 402 #define L_AGPIO3 79 // GPIO2_15 PINMUX_CTL 403 #define L_AGPIO8 84 // RESERVED 404 405 #define L_MGPIO0 85 // GPIO2_21 C_PINMUX_CTL offset: 0x0354 406 #define L_MGPIO1 86 // GPIO2_22 C_PINMUX_CTL 407 #define L_MGPIO2 87 // GPIO2_23 C_PINMUX_CTL 408 #define L_MGPIO3 88 // GPIO2_24 C_PINMUX_CTL 409 #define L_MGPIO4 89 // GPIO2_25 C_PINMUX_CTL 410 #define L_MGPIO5 90 // GPIO2_26 C_PINMUX_CTL 411 #define L_MGPIO6 91 // GPIO2_27 C_PINMUX_CTL 412 #define L_MGPIO7 92 // GPIO2_28 C_PINMUX_CTL 413 #define L_MGPIO8 93 // GPIO2_29 C_PINMUX_CTL 414 #define L_MGPIO9 94 // GPIO2_30 C_PINMUX_CTL 415 #define L_MGPIO10 95 // GPIO2_31 C_PINMUX_CTL 416 #define L_MGPIO11 96 // GPIO3_0 C_PINMUX_CTL 417 #define L_MGPIO12 97 // GPIO3_1 C_PINMUX_CTL 418 #define L_MGPIO13 98 // GPIO3_2 C_PINMUX_CTL 419 #define L_MGPIO14 99 // GPIO3_3 C_PINMUX_CTL 420 #define L_MGPIO15 100 // GPIO3_4 C_PINMUX_CTL 421 #define L_MGPIO16 101 // GPIO3_5 C_PINMUX_CTL 422 #define L_MGPIO17 102 // GPIO3_6 C_PINMUX_CTL 423 #define L_MGPIO18 103 // GPIO3_7 C_PINMUX_CTL 424 #define L_MGPIO19 104 // GPIO3_8 C_PINMUX_CTL 425 #define L_MGPIO31 104 // RESERVED 426 #define L_MGPIO47 104 // RESERVED 427 #define L_MGPIO57 104 // RESERVED 428 429 #define SYS_RSTN 105 430 #define RTC_CLK 106 431 #define ULP_GPIO0 107 // ULP_GPIO0 432 #define ULP_GPIO1 108 // ULP_GPIO1 433 #define ULP_GPIO2 109 // ULP_GPIO2 434 #define ULP_GPIO3 110 // ULP_GPIO3 435 #define PWR_HOLD 111 // ULP_GPIO4 436 #define HRESET 112 // ULP_GPIO5 437 #define SLEEP_N 113 // ULP_GPIO6 438 #define PMUIC_IRQ 114 // ULP_GPIO7 439 #define PIN_NONE 115 // used as invalid/unused PIN number 440 #define ULP_PIN SYS_RSTN 441 442 443 #define TCXO_COUNT_ENABLE YES 444 445 #define LOW_POWER_WR15_CS_ENHANCE YES 446 #define WATCHDOG_ROM_ENABLE YES 447 448 #define GPIO_WITH_ULP YES 449 #define GPIO_FUNC HAL_PIO_FUNC_GPIO 450 451 #define I2C_AUTO_SEND_STOP_CMD NO 452 #define I2C_WITH_BUS_RECOVERY YES 453 454 #define SPI_WITH_OPI NO 455 #define SPI_DMA_TRANSFER_NUM_BY_BYTE NO 456 457 #define DMA_TRANSFER_DEBUG YES 458 #define DMA_USE_HIDMA NO 459 #define DMA_WITH_MDMA YES // dma 460 #define DMA_WITH_SMDMA YES // Small dma 461 #define DMA_TRANS_BY_LLI NO 462 463 #define XIP_WITH_OPI YES 464 #define XIP_INT_BY_NMI YES 465 #define EFLASH_SLAVE_NOTIFY_MASTER_BOOTUP YES 466 467 #define ENABLE_CPU_TRACE 2 468 #define ADC_WITH_AUTO_SCAN YES 469 470 #define OTP_HAS_READ_PERMISSION YES 471 #define OTP_HAS_WRITE_PERMISSION YES 472 #define OTP_HAS_CLKLDO_VSET NO 473 474 #define SEC_IAMGE_AES_DECRYPT_EN NO 475 #define SEC_BOOT_SIGN_CHECK_EN YES 476 #define SEC_SUB_RST_BY_SECURITY_CORE NO 477 #define TRNG_WITH_SEC_COMMON YES 478 #define IS_MAIN_CORE YES 479 #define EXTERNAL_CLOCK_CALIBRATION YES 480 #define AON_SPECIAL_PIO YES 481 482 #define SUPPORT_HI_EMMC_PHY NO 483 484 #define OPI_PIN_FIX_DM1_DRIVER NO 485 #define OPI_USE_MCU_HS_CLK NO 486 #define QSPI0_FUNC HAL_PIO_FUNC_QSPI0 487 #define QSPI0_D0 S_MGPIO0 488 #define QSPI0_D1 S_MGPIO1 489 #define QSPI0_D2 S_MGPIO2 490 #define QSPI0_D3 S_MGPIO3 491 #define QSPI0_CLK S_MGPIO4 492 #define QSPI0_CS S_MGPIO5 493 494 #ifdef ATE_FLASH_CHECK 495 #define QSPI1_FUNC HAL_PIO_FUNC_QSPI0 496 #define QSPI1_D0 S_MGPIO0 497 #define QSPI1_D1 S_MGPIO1 498 #define QSPI1_D2 S_MGPIO2 499 #define QSPI1_D3 S_MGPIO3 500 #define QSPI1_CLK S_MGPIO4 501 #define QSPI1_CS S_MGPIO5 502 #else 503 #define QSPI1_FUNC HAL_PIO_FUNC_QSPI1 504 #define QSPI1_D0 S_MGPIO6 505 #define QSPI1_D1 S_MGPIO7 506 #define QSPI1_D2 S_MGPIO8 507 #define QSPI1_D3 S_MGPIO9 508 #define QSPI1_CLK S_MGPIO10 509 #define QSPI1_CS S_MGPIO11 510 #endif 511 512 #define XIP_EXIST YES 513 #define USE_XIP_INDEX 1 514 #define BCPU_INT0_ID 26 515 #define UART_BAUD_RATE_DIV_8 NO 516 #define FIXED_IN_ROM NO 517 #define PMU_LPM_WAKEUP_SRC_NUM 16 518 #define ENABLE_GPIO_INTERRUPT YES 519 #define CLK_AUTO_CG_ENABLE NO 520 #if defined(BUILD_APPLICATION_ROM) 521 #define BOOT_ROM_DFR_PRINT YES 522 #else 523 #define BOOT_ROM_DFR_PRINT NO 524 #endif 525 #define EFLASH_WRITE_CLK_DIV_AUTO_ADJ NO 526 #define DMA_WITH_MUX_CHANNEL YES 527 #define CRITICAL_INT_RESTORE YES 528 #define SEC_TRNG_ENABLE NO 529 #define DCACHE_IS_ENABLE NO 530 #define CODELOADER_SINGLE_PARTITION_EXP YES 531 #define AUXLDO_ENABLE_FLASH NO 532 #define TCXO_CLK_DYN_ADJUST NO 533 #define SUPPORT_PARTITION_FEATURE NO 534 #define SUPPORT_SINGLE_DSP_DUAL_IMAGE NO 535 /** 536 * @} 537 */ 538 #endif 539